公开(公告)号：US20160233894A1

公开(公告)日：2016-08-11

申请号：US15132143

申请日：2016-04-18

申请人： HGST Technologies Santa Ana, Inc.

发明人： Majid NEMATI ANARAKI ,  Xinde HU ,  Richard David BARNDT

IPC分类号： H03M13/45 ,  H03M13/00 ,  H03M13/11

CPC分类号： H03M13/1105 ,  H03M13/05 ,  H03M13/1111 ,  H03M13/1122 ,  H03M13/1128 ,  H03M13/114 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/255 ,  H03M13/458 ,  H03M13/615 ,  H03M13/6505

摘要： Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.

公开(公告)号：US20140337689A1

公开(公告)日：2014-11-13

申请号：US14339407

申请日：2014-07-23

申请人： Intel Corporation

发明人： Jawad B. KHAN

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G06F3/0608 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0641 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1048 ,  H03M13/1102 ,  H03M13/1162 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19 ,  H03M13/353

摘要： A method and system to improve the performance and/or reliability of a solid-state drive (SSD). In one embodiment of the invention, the SSD has logic compress a block of data to be stored in the SSD. If it is not possible to compress the block of data below the threshold, the SSD stores the block of data without any compression. If it is possible to compress the block of data below the threshold, the SSD compresses the block of data and stores the compressed data in the SSD. In one embodiment of the invention, the SSD has logic to dynamically adjust or select the strength of the error correcting code of the data that is stored in the SSD. In another embodiment of the invention, the SSD has logic to provide intra-page XOR protection of the data in the page.

摘要翻译： 一种提高固态硬盘（SSD）的性能和/或可靠性的方法和系统。 在本发明的一个实施例中，SSD具有逻辑压缩要存储在SSD中的数据块。 如果不可能压缩低于阈值的数据块，则SSD将不经任何压缩地存储数据块。 如果可以压缩低于阈值的数据块，则SSD压缩数据块并将压缩数据存储在SSD中。 在本发明的一个实施例中，SSD具有动态地调整或选择存储在SSD中的数据的纠错码的强度的逻辑。 在本发明的另一个实施例中，SSD具有为页面中的数据提供页内异或保护的逻辑。

公开(公告)号：USRE45043E1

公开(公告)日：2014-07-22

申请号：US13458412

申请日：2012-04-27

申请人： Bi-Woong Chung

发明人： Bi-Woong Chung

IPC分类号： H03M13/00 ,  H03M13/11

CPC分类号： H03M13/1162 ,  G11B20/10 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1151 ,  H03M13/1154 ,  H03M13/1177 ,  H03M13/3723

摘要： A method of decoding a received signal encoded with an LDPC code is provided. The method comprises initializing bits with an initial value of the received signal, obtaining posterior values of the bits by iteratively decoding the bits in a row direction and a column direction, determining on the basis of the posterior values whether an iterative decoding operation should be performed and comparing the posterior values with predetermined values and updating the initial value of the bits, when it is determined that the iterative decoding operation is be performed.

摘要翻译： 提供了一种用LDPC码编码的接收信号进行解码的方法。 该方法包括利用接收信号的初始值初始化比特，通过对行方向和列方向上的比特进行迭代解码来获得比特的后验值，根据后验值确定是否应执行迭代解码操作 并且当确定执行迭代解码操作时，将后验值与预定值进行比较并更新比特的初始值。

公开(公告)号：US08751912B1

公开(公告)日：2014-06-10

申请号：US12987419

申请日：2011-01-10

申请人： Nedeljko Varnica ,  Panu Chaichanavong ,  Heng Tang

发明人： Nedeljko Varnica ,  Panu Chaichanavong ,  Heng Tang

IPC分类号： H03M13/00 ,  G06F11/00

CPC分类号： H03M13/1105 ,  H03M13/036 ,  H03M13/1128 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/116 ,  H03M13/1162 ,  H03M13/6505 ,  H04L1/0051 ,  H04L1/0057

摘要： Apparatuses and methods associated with instant syndrome computation in a layered LDPC decoder are described. According to one embodiment, an apparatus includes a plurality of hardware layers, where a hardware layer is configured to compute a syndrome value from one or more bit values in the codeword. The apparatus includes a plurality of physical memories configured to store a plurality of syndrome values, where a physical memory is configured to store syndrome values computed by one or more hardware layers. The apparatus includes circuitry configured to simultaneously store a syndrome value computed by a hardware layer in physical memories associated with a bit in the codeword. The apparatus includes a decode logic configured to signal successful decoding of the codeword based, at least in part, on determining that a set of syndromes are satisfied based on values stored in the plurality of physical memories.

摘要翻译： 描述了在分层LDPC解码器中与即时综合征计算相关联的装置和方法。 根据一个实施例，一种装置包括多个硬件层，其中硬件层被配置为从码字中的一个或多个位值计算校正子值。 该装置包括多个物理存储器，被配置为存储多个校正子值，其中物理存储器被配置为存储由一个或多个硬件层计算的校正子值。 该装置包括被配置为同时存储由硬件层计算的与在码字中的位相关联的物理存储器中的校正子值的电路。 该装置包括解码逻辑，其被配置为基于至少部分地基于基于存储在多个物理存储器中的值来确定一组校正子来满足码字的成功解码。

公开(公告)号：US20140040700A1

公开(公告)日：2014-02-06

申请号：US13877650

申请日：2011-10-04

申请人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

发明人： Tomoyoshi Kobori ,  Steffen Kunze ,  Emil Matus ,  Gerhard Fettweis

IPC分类号： G06F11/10

CPC分类号： G06F11/1044 ,  G06F5/015 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/114 ,  H03M13/1145 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/2775 ,  H03M13/296 ,  H03M13/2978 ,  H03M13/6508 ,  H03M13/6513 ,  H03M13/6566 ,  H03M13/6569 ,  H03M13/6577

摘要： In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.

摘要翻译： 在能够同时处理多个纠错方法和多个码长的多核型纠错处理系统中，互连部分11具有延伸跨越多个纠错处理部分12a-12c的桶形移位器。 可以通过集体地使用多个纠错处理部分12a-12c的组或者通过单独地使用每个单独的纠错处理部分12a-12c来响应于互连配置信息来选择性地执行纠错处理。 利用这种结构，如果计算资源不足，则多个纠错处理部分12a-12c被共同使用，并且如果计算资源过多，则将空闲纠错处理部分分配给另一纠错处理部分。

公开(公告)号：US20120317459A1

公开(公告)日：2012-12-13

申请号：US13474095

申请日：2012-05-17

申请人： Engling Yeo ,  Zining Wu

发明人： Engling Yeo ,  Zining Wu

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/35 ,  G06F11/1048 ,  G11C16/3418 ,  G11C16/349 ,  H03M13/05 ,  H03M13/1102 ,  H03M13/1154 ,  H03M13/1162 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/23 ,  H03M13/2906 ,  H03M13/2939 ,  H03M13/2966 ,  H03M13/353 ,  H03M13/3715 ,  H04L1/0009 ,  H04L1/0059 ,  H04L1/0061

摘要： Systems and methods for adaptively operating a storage device are provided. A level of integrity of storing data in the storage device is determined. A coding scheme is selected based on the determined level of integrity of the storage device. An operation is performed on the storage device using the selected coding scheme.

摘要翻译： 提供了用于自适应地操作存储设备的系统和方法。 确定存储设备中存储数据的完整性水平。 基于确定的存储设备的完整性级别来选择编码方案。 使用所选择的编码方案对存储设备执行操作。

公开(公告)号：US08245106B2

公开(公告)日：2012-08-14

申请号：US12587419

申请日：2009-10-07

申请人： Xiao-Ming Chen ,  Oliver Theis ,  Marco Georgi

发明人： Xiao-Ming Chen ,  Oliver Theis ,  Marco Georgi

IPC分类号： G06F11/00

CPC分类号： H03M13/1162 ,  H03M13/1105 ,  H03M13/17 ,  H03M13/2906 ,  H03M13/43

摘要： For algebraic single symbol error correction and detection, a method is proposed which achieves correcting single symbol errors at unknown positions within codewords, identifying cases where multiple symbols within a codeword are uncorrectably corrupted, and identifying cases where a single symbol within a codeword is uncorrectably corrupted. The method comprises the steps of calculating a syndrome of a received word, splitting the syndrome into two parts, checking 3 integer weight quantities calculated from the two syndrome parts, converting the syndrome into a vector of integer valued “orthogonal bit error weights” associated to the received bits, and toggling those bits of the received word, where the associated “orthogonal bit error weight” is in the upper half of its possible value range.

摘要翻译： 对于代数单符号纠错和检测，提出一种方法，其实现在码字内的未知位置处校正单符号错误，识别码字内的多个符号不可纠错地损坏的情况，以及识别码字内的单个符号不可修正地损坏的情况 。 该方法包括以下步骤：计算接收到的词的综合征，将所述综合征分为两部分，检查从所述两个综合征部分计算的3个整数权重量，将所述校正子转换为与所述校正子相关联的整数值“正交位错误权重”的向量 接收到的比特，并且切换接收到的字的那些比特，其中相关联的“正交比特误差权重”在其可能的值范围的上半部分。

公开(公告)号：US08230298B2

公开(公告)日：2012-07-24

申请号：US12651453

申请日：2010-01-01

申请人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

发明人： Hau Thien Tran ,  Kelly Brian Cameron ,  Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/1162 ,  H03M13/1117 ,  H03M13/112 ,  H03M13/1122 ,  H03M13/1125 ,  H03M13/1137 ,  H03M13/114 ,  H03M13/1165 ,  H03M13/1185 ,  H03M13/616 ,  H03M13/6505 ,  H03M13/658 ,  H03M13/6583

摘要： Overlapping sub-matrix based LDPC (Low Density Parity Check) decoder. Novel decoding approach is presented, by which, updated bit edge messages corresponding to a sub-matrix of an LDPC matrix are immediately employed for updating of the check edge messages corresponding to that sub-matrix without requiring storing the bit edge messages; also updated check edge messages corresponding to a sub-matrix of the LDPC matrix are immediately employed for updating of the bit edge messages corresponding to that sub-matrix without requiring storing the check edge messages. Using this approach, twice as many decoding iterations can be performed in a given time period when compared to a system that performs updating of all check edge messages for the entire LDPC matrix, then updating of all bit edge messages for the entire LDPC matrix, and so on. When performing this overlapping approach in conjunction with min-sum processing, significant memory savings can also be achieved.

公开(公告)号：US20120185757A1

公开(公告)日：2012-07-19

申请号：US13352941

申请日：2012-01-18

申请人： Hong-Sil JEONG ,  Sung-Ryul YUN ,  Hyun-Koo YANG ,  Alain MOURAD ,  Ismael GUTIERREZ

发明人： Hong-Sil JEONG ,  Sung-Ryul YUN ,  Hyun-Koo YANG ,  Alain MOURAD ,  Ismael GUTIERREZ

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/1148 ,  H03M13/1162 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/17 ,  H03M13/253 ,  H03M13/255 ,  H03M13/2906 ,  H03M13/2957 ,  H03M13/618 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/6393 ,  H03M13/6552 ,  H04L1/0008 ,  H04L1/0013

摘要： An apparatus and method for transmitting and receiving data in a wireless communication is provided. The method includes determining a number of zero-padding bits, determining a number (Npad) of bit groups in which all bits are padded with zeros, padding the all bits within 0th to (Npad−1)th bit groups indicated by a shortening pattern with zeros, mapping information bits to bit positions which are not padded in Bose Chaudhuri Hocquenghem (BCH) information bits, BCH encoding the BCH information bits to generate Low Density Parity Check (LDPC) information bits, and LDPC encoding the LDPC information bits to generate a zero-padded codeword, wherein the shortening pattern is defined as an order of bit groups defined as 6, 5, 4, 9, 3, 2, 1, 8, 0, 7, 10 and 11.

摘要翻译： 提供了一种用于在无线通信中发送和接收数据的装置和方法。 该方法包括确定零填充比特数，确定其中所有比特用零填补的比特组的数量（Npad），填充由缩短模式指示的第0到第（Npad-1）比特组内的所有比特 使用零，将信息位映射到在Bose Chaudhuri Hocquenghem（BCH）信息比特中未填充的比特位置，BCH编码BCH信息比特以生成低密度奇偶校验（LDPC）信息比特，并且LDPC编码LDPC信息比特以生成 零填充码字，其中缩短模式被定义为定义为6,5,4,9,3,2,1,8,10,7,10和11的位组的顺序。

公开(公告)号：US20110167315A1

公开(公告)日：2011-07-07

申请号：US13047471

申请日：2011-03-14

申请人： Gyu-Bum KYUNG ,  Hong-Sil JEONG ,  Jae-Yoel KIM ,  Sung-Eun Park ,  Kyeong-Cheol YANG ,  Se-Ho MYLING

发明人： Gyu-Bum KYUNG ,  Hong-Sil JEONG ,  Jae-Yoel KIM ,  Sung-Eun Park ,  Kyeong-Cheol YANG ,  Se-Ho MYLING

IPC分类号： H03M13/11 ,  G06F11/10

CPC分类号： H03M13/1105 ,  H03M13/1102 ,  H03M13/1151 ,  H03M13/1162 ,  H03M13/1171 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/1194

摘要： A system and method for processing a block Low Density Parity Check (LDPC) code are provided. The system includes, a decoding apparatus for decoding a block LDPC code using a parity check matrix, the parity check matrix including an information part and a parity part, the parity part including a first section (B) including a plurality of first permutation matrices, a second section (D) including a second permutation matrix, a third section (T) including a plurality of identity matrices (I) arranged diagonally within the third section and a plurality of third permutation matrices arranged below the plurality of identity matrices, and a fourth section (E) including a fourth permutation matrix.

摘要翻译： 提供了一种用于处理块低密度奇偶校验（LDPC）码的系统和方法。 该系统包括：使用奇偶校验矩阵解码块LDPC码的解码装置，奇偶校验矩阵包括信息部分和奇偶校验部分，奇偶校验部分包括包括多个第一置换矩阵的第一部分（B） 包括第二置换矩阵的第二部分（D），包括在第三部分内对角排列的多个单位矩阵（I）的第三部分（T）和布置在多个单位矩阵之下的多个第三置换矩阵，以及 第四部分（E）包括第四置换矩阵。