公开(公告)号：US09143147B1

公开(公告)日：2015-09-22

申请号：US14323821

申请日：2014-07-03

Applicant: Keysight Technologies, Inc.

Inventor： Sourja Ray ,  John Patrick Keane

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1023 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215

Abstract: An analog input signal is dithered using a dithering sequence and then partially chopped using a chopping sequence. The dithered and partially chopped signal is then digitized by analog-to-digital converter (ADC) slices operating in alternating fashion, and the resulting digitized signals are adjusted according to the dithering sequence and the chopping sequence to compensate for gain and voltage offset errors of the ADC slices.

Abstract translation: 使用抖动序列对模拟输入信号进行抖动，然后使用斩波序列进行部分切割。 然后，抖动和部分切碎的信号通过以交替方式操作的模数转换器（ADC）片数字化，并且根据抖动序列和斩波序列调整所得到的数字化信号以补偿增益和电压偏移误差 ADC切片。

公开(公告)号：US20150171890A1

公开(公告)日：2015-06-18

申请号：US14629442

申请日：2015-02-23

Applicant: Syntropy Systems, LLC

Inventor： Christopher Pagnanelli

IPC: H03M3/00 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03M3/468 ,  H03M1/0836 ,  H03M1/121

Abstract: Provided is an apparatus for converting a continuous-time, continuously variable signal into a sampled and quantized signal, which includes an input line for accepting an input signal, multiple processing branches coupled to the input line, and an adder coupled to outputs of the plurality of processing branches. Each of the processing branches includes a sampling/quantization circuit and a digital bandpass interpolation filter having an input coupled to an output of the sampling/quantization circuit. The digital bandpass interpolation filters in different ones of the processing branches have frequency responses that are centered at different frequencies. The digital bandpass interpolation filter in at least one of the processing branches includes: (i) a quadrature downconverter, (ii) a first lowpass filter and a second lowpass filter, (iii) a first interpolator and a second interpolator, each having an input for inputting a variable interpolant value, and (iv) a quadrature upconverter.

Abstract translation: 提供了一种用于将连续时间连续可变信号转换为采样和量化信号的装置，其包括用于接受输入信号的输入线，耦合到输入线的多个处理分支和耦合到多个输出的输出的加法器 的处理分支机构。 每个处理分支包括具有耦合到采样/量化电路的输出的输入的采样/量化电路和数字带通内插滤波器。 不同处理分支中的数字带通插值滤波器具有以不同频率为中心的频率响应。 至少一个处理分支中的数字带通插值滤波器包括：（i）正交下变频器，（ii）第一低通滤波器和第二低通滤波器，（iii）第一内插器和第二内插器，每个具有输入 用于输入可变内插值，和（iv）正交上变频器。

公开(公告)号：US20140266823A1

公开(公告)日：2014-09-18

申请号：US14209848

申请日：2014-03-13

Applicant: Integrated Device Technology, Inc.

Inventor： Arnaud Biallais ,  Fatima Ghanem

IPC: H03M1/08

CPC classification number: H03M1/0609 ,  H03M1/0607 ,  H03M1/08 ,  H03M1/109 ,  H03M1/121 ,  H03M1/1215

Abstract: The present disclosure relates to the field of background estimation in a time-interleaved analog-to-digital converter (ADC). More specifically, the present disclosure relates to systems and methods for background estimation of offset and gain errors in a time-interleaved ADC based on sample count. The error estimation unit of the time-interleaved ADC system includes a counting unit, a subtractor and an integrator. The method for estimating an offset error in a time-interleaved ADC includes determining signs of the signals and outputting corresponding values by the counting unit. The values are further compared and integrated to estimate the offset error. The method for estimating a gain error in a time-interleaved ADC includes determining the absolute values of the signals and comparing the absolute values with a predetermined threshold value. The comparison results are further integrated to estimate the gain error.

Abstract translation: 本公开涉及时间交织的模数转换器（ADC）中的背景估计领域。 更具体地，本公开涉及用于基于样本计数的时间交织ADC中的偏移和增益误差的背景估计的系统和方法。 时间交织的ADC系统的误差估计单元包括计数单元，减法器和积分器。 用于估计时间交替ADC中的偏移误差的方法包括确定信号的符号并由计数单元输出相应的值。 进一步比较和积分这些值以估计偏移误差。 用于估计时间交替ADC中的增益误差的方法包括确定信号的绝对值并将绝对值与预定阈值进行比较。 比较结果被进一步整合以估计增益误差。

公开(公告)号：US08742749B2

公开(公告)日：2014-06-03

申请号：US13116234

申请日：2011-05-26

Applicant: Daniel G. Knierim

Inventor： Daniel G. Knierim

IPC: G01R23/14

CPC classification number: H03M1/121 ,  G01R13/0272

Abstract: A test and measurement instrument including a splitter configured to split an input signal having a particular bandwidth into a plurality of split signals, each split signal including substantially the entire bandwidth of the input signal; a plurality of harmonic mixers, each harmonic mixer configured to mix an associated split signal of the plurality of split signals with an associated harmonic signal to generate an associated mixed signal; and a plurality of digitizers, each digitizer configured to digitize a mixed signal of an associated harmonic mixer of the plurality of harmonic mixers. A first-order harmonic of at least one harmonic signal associated with the harmonic mixers is different from an effective sample rate of at least one of the digitizers.

Abstract translation: 一种测试和测量仪器，包括分配器，其被配置为将具有特定带宽的输入信号分割成多个分离信号，每个分离信号基本上包括输入信号的整个带宽; 多个谐波混合器，每个谐波混频器被配置为将所述多个分离信号的相关联的分离信号与相关联的谐波信号混合以产生相关联的混合信号; 以及多个数字转换器，每个数字转换器被配置为数字化多个谐波混频器中相关联的谐波混频器的混合信号。 与谐波混频器相关联的至少一个谐波信号的一阶谐波与至少一个数字化仪的有效采样率不同。

公开(公告)号：US08648742B2

公开(公告)日：2014-02-11

申请号：US13406509

申请日：2012-02-27

Applicant: Mohammad A. Khajehnejad ,  Babak Hassibi ,  Juhwan Yoo

Inventor： Mohammad A. Khajehnejad ,  Babak Hassibi ,  Juhwan Yoo

IPC: H03M1/12

CPC classification number: H03M1/1265 ,  H03M1/121 ,  H03M7/3062

Abstract: Systems and methods in accordance with embodiments of the invention utilize a CS architecture based on a sub-linear time recovery process (with reduced memory requirements). In several embodiments, a novel structured measurement matrix is exploited during signal acquisition allowing the use of a recovery process based on relatively simple computational primitives making it more amenable to implementation in a fully-integrated form. One embodiment of the invention includes an analog front end configured to receive an analog input signal, and CS sampling circuitry connected to an output of the analog front end and configured to generate a plurality of measurements using a structured measurement matrix, where each row of the structured measurement matrix is generated using a different predetermined check node. In addition, the CS sampling circuitry is configured to generate the plurality of measurements at a rate that is less than the Nyquist rate of the analog input signal.

Abstract translation: 根据本发明的实施例的系统和方法利用基于亚线性时间恢复过程（具有减少的存储器要求）的CS架构。 在几个实施例中，在信号获取期间利用新颖的结构化测量矩阵，允许使用基于相对简单的计算原语的恢复过程，使得更适合以完全集成的形式实现。 本发明的一个实施例包括被配置为接收模拟输入信号的模拟前端和连接到模拟前端的输出并被配置为使用结构化测量矩阵生成多个测量的CS采样电路，其中， 使用不同的预定校验节点生成结构化测量矩阵。 另外，CS采样电路被配置为以小于模拟输入信号的奈奎斯特速率的速率产生多个测量。

公开(公告)号：US08583390B2

公开(公告)日：2013-11-12

申请号：US13282552

申请日：2011-10-27

Applicant: Peter J Pupalaikis ,  David C Graef

Inventor： Peter J Pupalaikis ,  David C Graef

IPC: G01R19/25 ,  G01R13/02 ,  G06F19/00 ,  G06F17/40

CPC classification number: H03M1/121 ,  G01R13/02 ,  G01R13/0272 ,  G01R19/25 ,  G06F17/40 ,  G06F19/00 ,  H03M1/60

Abstract: A method for improving bandwidth of an oscilloscope involves, in preferred embodiments, the use of frequency up-conversion and down-conversion techniques. In an illustrative embodiment the technique involves separating an input signal into a high frequency content and a low frequency content, down-converting the high frequency content in the analog domain so that it may be processed by the oscilloscope's analog front end, digitizing the low frequency content and the down-converted high frequency content, and forming a digital representation of the received analog signal from the digitized low frequency content and high frequency content.

Abstract translation: 在优选实施例中，用于提高示波器的带宽的方法涉及使用上变频和下变频技术。 在说明性实施例中，该技术涉及将输入信号分离成高频内容和低频内容，对模拟域中的高频内容进行下变频，使得其可以由示波器的模拟前端处理，数字化低频 内容和下变频高频内容，并且从数字化的低频内容和高频内容形成接收的模拟信号的数字表示。

公开(公告)号：US20130278295A1

公开(公告)日：2013-10-24

申请号：US13770337

申请日：2013-02-19

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  GEORGIA TECH RESEARCH CORPORATION

Inventor： Sung Yeol KIM ,  Hyun Woo CHOI ,  Nicholas TZOU ,  Xian WANG ,  Thomas MOON ,  Abhijit CHATTERJEE ,  Ho Sun YOO

IPC: H03M1/12 ,  H03B21/00

CPC classification number: H03M1/1245 ,  H03B21/00 ,  H03M1/121

Abstract: An apparatus for measuring a high speed signal may comprise a plurality of Analog-Digital converters (AD converter) that are arranged in parallel to each other to sample an input signal at different frequencies; a plurality of frequency synthesizers configured to provide each AD converter with a different sampling frequency; a signal processor configured to receive an output of the plurality of AD converters to reconstruct the input signal; and/or a controller configured to receive and process a trigger signal.

Abstract translation: 用于测量高速信号的装置可以包括彼此并联布置以对不同频率的输入信号进行采样的多个模数转换器（AD转换器）; 多个频率合成器，被配置为向每个AD转换器提供不同的采样频率; 信号处理器，被配置为接收所述多个AD转换器的输出以重建所述输入信号; 和/或被配置为接收和处理触发信号的控制器。

公开(公告)号：US08547160B2

公开(公告)日：2013-10-01

申请号：US13712522

申请日：2012-12-12

Applicant: Fujitsu Semiconductor Limited

Inventor： Ian Juso Dedic ,  Gavin Lambertus Allen

IPC: H03K17/00

CPC classification number: H03M1/0614 ,  G11C27/02 ,  H01H9/54 ,  H03K17/00 ,  H03L7/00 ,  H03L7/091 ,  H03M1/002 ,  H03M1/0881 ,  H03M1/1009 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1245 ,  H03M1/126 ,  Y10T307/76

Abstract: There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line.

公开(公告)号：US08482445B1

公开(公告)日：2013-07-09

申请号：US13556107

申请日：2012-07-23

Applicant: Fredric J. Harris

Inventor： Fredric J. Harris

IPC: H03M1/12

CPC classification number: H03M1/10 ,  H03M1/1038 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/1225

Abstract: A two-channel time-interleaved analog-to-digital converter (TI-ADC) for communication signals offers a significant increase in the available sample rate of ADCs. Its performance is degraded by timing and gain mismatches. Both timing and gain mismatches are corrected in the digital data section of a two-channel TI-ADC for band-pass input signals. This is a realistic communications system scenario as modern system designs lean towards having the ADC interface with intermediate frequency (IF) signal in the analog section of a digital receiver rather than in the DC centered, analog down converted, in-phase and quadrature pair.

Abstract translation: 用于通信信号的双通道时间交织模数转换器（TI-ADC）可显着提高ADC的可用采样率。 其性能因时序和增益不匹配而降低。 定时和增益不匹配在双通道TI-ADC的数字数据部分中进行了纠错，用于带通输入信号。 这是一个现实的通信系统场景，因为现代系统设计倾向于在数字接收机的模拟部分中将ADC接口与中频（IF）信号相比，而不是以直流中心，模拟下变频，同相和正交对为对象。

公开(公告)号：US20120299579A1

公开(公告)日：2012-11-29

申请号：US13116234

申请日：2011-05-26

Applicant: Daniel G. KNIERIM

Inventor： Daniel G. KNIERIM

IPC: G01R23/14 ,  G06G7/16

CPC classification number: H03M1/121 ,  G01R13/0272

Abstract: A test and measurement instrument including a splitter configured to split an input signal having a particular bandwidth into a plurality of split signals, each split signal including substantially the entire bandwidth of the input signal; a plurality of harmonic mixers, each harmonic mixer configured to mix an associated split signal of the plurality of split signals with an associated harmonic signal to generate an associated mixed signal; and a plurality of digitizers, each digitizer configured to digitize a mixed signal of an associated harmonic mixer of the plurality of harmonic mixers. A first-order harmonic of at least one harmonic signal associated with the harmonic mixers is different from an effective sample rate of at least one of the digitizers.

Abstract translation: 一种测试和测量仪器，包括分配器，其被配置为将具有特定带宽的输入信号分割成多个分离信号，每个分离信号基本上包括输入信号的整个带宽; 多个谐波混合器，每个谐波混频器被配置为将所述多个分离信号的相关联的分离信号与相关联的谐波信号混合以产生相关联的混合信号; 以及多个数字转换器，每个数字转换器被配置为数字化多个谐波混频器中相关联的谐波混频器的混合信号。 与谐波混频器相关联的至少一个谐波信号的一阶谐波与至少一个数字化仪的有效采样率不同。