公开(公告)号：US20140016395A1

公开(公告)日：2014-01-16

申请号：US14030619

申请日：2013-09-18

Applicant: Panasonic Corporation

Inventor： Yukihiro KANEKO

IPC: G11C11/22

CPC classification number: G11C11/2275 ,  G11C5/025 ,  G11C11/22 ,  G11C11/5657 ,  G11C2013/0092 ,  H01L21/28291 ,  H01L29/516 ,  H01L29/78391 ,  H04L29/12

Abstract: Pulse voltages V1 and V2 are applied to the first upper gate electrode and the second upper gate electrode, respectively, for a period T1 which is shorter than a period necessary to invert all the polarizations included in the ferroelectric film, while voltages Vs, Vd, and V3 are applied to the source electrode, the drain electrode, and the lower gate electrode film, respectively, so as to increase the values of the widths WRH1 and WRH2 and so as to decrease the value of the width WRL. The pulse voltages V1 and V2 have a smaller voltage than a voltage necessary to invert all the polarizations included in the ferroelectric film. The voltage Vs, the voltage Vd, the voltage V3, the pulse voltage V1, and the pulse voltage V2 satisfy the following relationship: Vs, Vd, V3

Abstract translation: 脉冲电压V1和V2分别施加到第一上栅极电极和第二上栅电极，周期T1短于反转铁电体中包含的所有极化所需的周期，同时电压Vs，Vd， 并且V3分别施加到源电极，漏电极和下栅极电极膜，以便增加宽度WRH1和WRH2的值，并且减小宽度WRL的值。 脉冲电压V1和V2具有比包含在铁电体膜中的所有极化反转所必需的电压更小的电压。 电压Vs，电压Vd，电压V3，脉冲电压V1，脉冲电压V2满足Vs，Vd，V3

公开(公告)号：US08565001B2

公开(公告)日：2013-10-22

申请号：US13240225

申请日：2011-09-22

Applicant: Yukihiro Kaneko

Inventor： Yukihiro Kaneko

IPC: G11C11/22

CPC classification number: H01L27/10 ,  G11C11/22 ,  G11C11/5657 ,  H01L27/101 ,  H01L27/11502 ,  H01L29/7869

Abstract: A method of flowing a current selectively with a nonvolatile switching device according to the present disclosure includes a step of configuring, in the nonvolatile switching device, any one of a first state in which a current does not flow between the electrode group, a second state in which a current flows selectively between the first electrode and the second electrode, and a third state in which a current flows selectively between the first electrode and the third electrode. When any one of the first state, the second state and the third state is configured, voltages V1, Va, Vb and Vc, which satisfy predetermined inequality set corresponding to the one of the first to third states, are applied to the control electrode, the first electrode, the second electrode, and the third electrode, respectively.

Abstract translation: 根据本发明的一种使用非易失性开关器件选择性地流动电流的方法包括在非易失性开关器件中配置电流不在电极组之间的第一状态中的任何一种，第二状态 其中电流选择性地在第一电极和第二电极之间流动，并且电流在第一电极和第三电极之间选择性地流动的第三状态。 当配置第一状态，第二状态和第三状态中的任何一个时，满足对应于第一至第三状态之一的预定不等式的电压V1，Va，Vb和Vc被施加到控制电极， 第一电极，第二电极和第三电极。

公开(公告)号：US20120008365A1

公开(公告)日：2012-01-12

申请号：US13240225

申请日：2011-09-22

Applicant: Yukihiro KANEKO

Inventor： Yukihiro KANEKO

IPC: G11C11/22

CPC classification number: H01L27/10 ,  G11C11/22 ,  G11C11/5657 ,  H01L27/101 ,  H01L27/11502 ,  H01L29/7869

Abstract: A method of flowing a current selectively with a nonvolatile switching device according to the present disclosure includes a step of configuring, in the nonvolatile switching device, any one of a first state in which a current does not flow between the electrode group, a second state in which a current flows selectively between the first electrode and the second electrode, and a third state in which a current flows selectively between the first electrode and the third electrode. When any one of the first state, the second state and the third state is configured, voltages V1, Va, Vb and Vc, which satisfy predetermined inequality set corresponding to the one of the first to third states, are applied to the control electrode, the first electrode, the second electrode, and the third electrode, respectively.

Abstract translation: 根据本发明的一种使用非易失性开关器件选择性地流动电流的方法包括在非易失性开关器件中配置电流不在电极组之间的第一状态中的任何一种，第二状态 其中电流选择性地在第一电极和第二电极之间流动，并且电流在第一电极和第三电极之间选择性地流动的第三状态。 当配置第一状态，第二状态和第三状态中的任何一个时，满足对应于第一至第三状态之一的预定不等式的电压V1，Va，Vb和Vc被施加到控制电极， 第一电极，第二电极和第三电极。

公开(公告)号：US08023308B1

公开(公告)日：2011-09-20

申请号：US07582615

申请日：1990-09-14

Applicant: Joseph T. Evans, Jr. ,  William D. Miller ,  Richard H. Womack

Inventor： Joseph T. Evans, Jr. ,  William D. Miller ,  Richard H. Womack

IPC: G11C7/00 ,  G11C11/22

CPC classification number: G11C11/22 ,  G11C11/5657

Abstract: A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.

Abstract translation: 非易失性存储单元及相关系统利用铁电电容器作为数据存储元件。 提供电路用于写入单个铁电电容器存储元件以及反向运行的双重存储元件。 通过使用自动恢复原始数据状态的配置的读出放大器来读取存储元件，从而不再需要后续的恢复操作。 描述了包括用于驱动位线，字线和驱动线以实现写入和读取操作的电路的存储器系统。

公开(公告)号：US07889628B2

公开(公告)日：2011-02-15

申请号：US12128788

申请日：2008-05-29

Applicant: Hyoung-soo Ko ,  Eun-sik Kim ,  Sung-dong Kim ,  Ju-hwan Jung ,  Hong-sik Park ,  Chul-min Park ,  Seung-bum Hong

Inventor： Hyoung-soo Ko ,  Eun-sik Kim ,  Sung-dong Kim ,  Ju-hwan Jung ,  Hong-sik Park ,  Chul-min Park ,  Seung-bum Hong

IPC: G11B7/00

CPC classification number: G11B9/02 ,  G11C11/5657 ,  Y10S977/947

Abstract: A ferroelectric recording medium and a writing method for the same are provided. The ferroelectric recording medium includes a ferroelectric layer which reverses its polarization when receiving a predetermined coercive voltage. A nonvolatile anisotrophic conduction layer is formed on the ferroelectric layer. A resistance of the anisotrophic conduction layer decreases when receiving a first voltage lower than the coercive voltage, and the resistance of the anisotrophic conduction layer increases when receiving a second voltage higher than the coercive voltage. Multi-bit information is stored by a combination of polarization states of the ferroelectric layer and the resistance of the anisotrophic conduction layer. Accordingly, multiple bits can be expressed on one domain of the ferroelectric recording medium.

Abstract translation: 提供铁电记录介质及其写入方法。 铁电记录介质包括在接收预定的矫顽电压时反转其极化的铁电层。 在铁电层上形成非挥发性各向异性导电层。 当接收到低于矫顽电压的第一电压时，各向异性传导层的电阻降低，并且当接收到高于矫顽电压的第二电压时，各向异性导电层的电阻增加。 通过铁电层的极化状态和各向异性导电层的电阻的组合来存储多位信息。 因此，可以在铁电记录介质的一个域上表示多个位。

公开(公告)号：US07672151B1

公开(公告)日：2010-03-02

申请号：US07377168

申请日：1989-07-10

Applicant: Joseph T. Evans, Jr. ,  William D. Miller ,  Richard H. Womack

Inventor： Joseph T. Evans, Jr. ,  William D. Miller ,  Richard H. Womack

IPC: G11C7/00 ,  G11C11/22

CPC classification number: G11C11/22 ,  G11C11/5657

Abstract: A non-volatile memory cell and related system utilize ferroelectric capacitors as data storage elements. Circuitry is provided for writing to a single ferroelectric capacitor storage element, as well as to dual storage elements operating inversely. The storage elements are read by use of a sense amplifier in a configuration which automatically restores the original data states, thereby eliminating the need for a subsequent restore operation. Memory systems are described which include circuitry for driving bit lines, word lines and drive lines to accomplish both the write and read operations.

Abstract translation: 非易失性存储单元及相关系统利用铁电电容器作为数据存储元件。 提供电路用于写入单个铁电电容器存储元件以及反向运行的双重存储元件。 通过使用自动恢复原始数据状态的配置的读出放大器来读取存储元件，从而不再需要后续的恢复操作。 描述了包括用于驱动位线，字线和驱动线以实现写入和读取操作的电路的存储器系统。

公开(公告)号：US20090268506A1

公开(公告)日：2009-10-29

申请号：US12110099

申请日：2008-04-25

Applicant: Michael Allen Seigler ,  Oleg N. Mryasov

Inventor： Michael Allen Seigler ,  Oleg N. Mryasov

IPC: G11C11/00

CPC classification number: G11C11/5657 ,  G11C11/22 ,  G11C11/2273 ,  G11C11/56 ,  G11C11/5671 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C2213/54 ,  G11C2213/56

Abstract: In a particular illustrative embodiment, a storage device includes a controller and a plurality of resistive elementary memory cells accessible via the controller. Each resistive elementary memory cell of the plurality of resistive elementary memory cells includes a plurality of memory layers selected to have hysteretic properties to store multiple data values.

Abstract translation: 在特定说明性实施例中，存储设备包括控制器和经由控制器可访问的多个电阻性基本存储器单元。 多个电阻基本存储器单元中的每个电阻基本存储单元包括被选择具有滞后特性以存储多个数据值的多个存储器层。

公开(公告)号：US20090059648A1

公开(公告)日：2009-03-05

申请号：US12201349

申请日：2008-08-29

Applicant: Susumu SHUTO

Inventor： Susumu SHUTO

IPC: G11C11/22 ,  G11C11/24 ,  G11C11/409

CPC classification number: G11C11/22 ,  G11C11/5657

Abstract: This ferroelectric semiconductor storage device includes: a ferroelectric capacitor; and a transistor having one end of its current path connected to one electrode of the ferroelectric capacitor. A plate line is connected to the other electrode of the ferroelectric capacitor. A word line is connected to the gate of the transistor. A bit line is connected to the other electrode of a capacitor and the other end of the transistor, the capacitor having its one electrode connected to the ground. A bit line potential detection circuit detects a potential of the bit line. A connection circuit provides the same potential between a potential of the plate line and a potential of the bit line based on an output from the bit line potential detection circuit.

Abstract translation: 该铁电半导体存储装置包括：铁电电容器; 以及其电流路径的一端连接到铁电体电容器的一个电极的晶体管。 板线连接到铁电电容器的另一个电极。 字线连接到晶体管的栅极。 位线连接到电容器的另一个电极，晶体管的另一端连接到电容器，其一个电极连接到地。 位线电位检测电路检测位线的电位。 连接电路基于位线电位检测电路的输出，在板线的电位和位线的电位之间提供相同的电位。

公开(公告)号：US07440307B2

公开(公告)日：2008-10-21

申请号：US11584491

申请日：2006-10-23

Applicant: Yoshiki Murayama ,  Shigeharu Matsushita

Inventor： Yoshiki Murayama ,  Shigeharu Matsushita

IPC: G11C11/22

CPC classification number: G11C11/22 ,  G11C11/223 ,  G11C11/5657

Abstract: This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and the first word line and between the bit line and the second word line respectively at least on a region where the bit line and the first and second word lines intersect with each other. The bit line, the first word line and the first ferroelectric film constitute a first ferroelectric capacitor while the bit line, the second word line and the second ferroelectric film constitute a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor constitute a memory cell.

Abstract translation: 该存储器包括位线，第一字线和第二字线，其被布置成在保持位线之间与位线相交并且具有电容彼此不同的第一铁电体膜和第二铁电体膜，第一铁电体膜和第二铁电体膜布置在 至少在位线和第一和第二字线彼此相交的区域上分别位于第一字线和第一字线之间以及位线与第二字线之间。 位线，第一字线和第一铁电体膜构成第一铁电电容器，而位线，第二字线和第二铁电体膜构成第二铁电电容器，并且第一铁电电容器和第二铁电电容器构成 记忆单元

公开(公告)号：US07360144B2

公开(公告)日：2008-04-15

申请号：US11320959

申请日：2005-12-30

Applicant: Hee Bok Kang ,  Jin Hong Ahn

Inventor： Hee Bok Kang ,  Jin Hong Ahn

IPC: G11C29/00

CPC classification number: G11C11/5657 ,  G11C7/1006 ,  G11C11/22 ,  G11C29/4401 ,  G11C2029/0409

Abstract: A multi-bit nonvolatile ferroelectric memory device comprises a plurality of memory cell arrays each including a plurality of multi-bit unit cells connected serially, and a correcting block adapted and configured to group the predetermined number of multi-bit unit cells in one memory group to store a data level signal corresponding to the same multi-bit data in each memory group at a write mode, and to convert data level signals of the selected memory group at a read mode into the multi-bit data and compare the multi-bit data in each bit to identify the same data bit as an effective data bit. As a result, the multi-bit nonvolatile ferroelectric memory device includes a fail cell repair circuit to effectively process randomly distributed cell data.

Abstract translation: 多位非易失性铁电存储器件包括多个存储单元阵列，每个存储单元阵列包括串行连接的多个多位单位单元，以及一个适配和配置为将预定数量的多位单元单元分组在一个存储器组中的校正块 以写模式存储与每个存储器组中相同的多位数据相对应的数据电平信号，并将读出模式下所选存储器组的数据电平信号转换为多位数据，并将多位数据 每个位中的数据标识与有效数据位相同的数据位。 结果，多位非易失性铁电存储器件包括有效处理随机分布的单元数据的故障单元修复电路。