公开(公告)号：US20110309859A1

公开(公告)日：2011-12-22

申请号：US13221029

申请日：2011-08-30

Applicant: Yukihiro KANEKO

Inventor： Yukihiro KANEKO

IPC: H03K19/185

CPC classification number: H01L27/101 ,  G11C11/22 ,  H01L27/11502

Abstract: In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The semiconductor layer is disposed on a ferroelectric layer. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first and second input electrode, respectively, a step of measuring current generated by applying the voltage between the electric current source electrode and the output electrode to determine, on the basis of the measured current, which of the high or low resistant state the non-volatile logic circuit has.

Abstract translation: 在非易失性逻辑电路中，第一输入电极和第二输入电极形成在半导体层上并且在平面图中介于电流源电极和输出电极之间。 半导体层设置在铁电层上。 一种操作非易失性逻辑电路的方法包括通过分别向第一和第二输入电极施加电压来写入从四种状态中选出的一种状态的步骤，测量通过在电流源电极 所述输出电极根据所测量的电流来确定所述非易失性逻辑电路具有的高电阻或低电阻状态。

公开(公告)号：US20130009714A1

公开(公告)日：2013-01-10

申请号：US13614624

申请日：2012-09-13

Applicant: Yu NISHITANI ,  Yukihiro KANEKO ,  Michihito UEDA

Inventor： Yu NISHITANI ,  Yukihiro KANEKO ,  Michihito UEDA

IPC: H03B5/24

CPC classification number: H03B5/20 ,  H01L27/0682 ,  H01L28/20 ,  H01L28/40 ,  H01L28/56 ,  H03B5/24 ,  H03B2200/004 ,  H03B2201/02 ,  H03B2201/0208

Abstract: A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, each of which comprises a resistance and a capacitor. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitor. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film.

Abstract translation: 电阻 - 电容振荡电路包括放大器和移相电路。 相移电路包括至少三个电阻 - 电容电路元件，每个电阻电容元件包括电阻和电容器。 电阻 - 电容电路元件中的至少一个包括可变电阻和可变电容。 可变电阻由第一电极，第二电极，半导体膜的一部分，铁电体膜的一部分和第四电极形成。 可变电容器由第二电极，第三电极，第五电极，铁电体膜的另一部分，半导体膜的另一部分和顺电膜形成。

公开(公告)号：US20090290404A1

公开(公告)日：2009-11-26

申请号：US12405799

申请日：2009-03-17

Applicant: Yukihiro KANEKO ,  Yoshihisa Kato

Inventor： Yukihiro KANEKO ,  Yoshihisa Kato

IPC: G11C11/22 ,  G11C11/00 ,  H01L27/115

CPC classification number: G11C11/22 ,  G11C11/5657 ,  H01L27/1159 ,  H01L27/11597 ,  H01L27/12 ,  H01L29/6684 ,  H01L29/78391

Abstract: A memory cell includes a memory element including a MFSFET having a gate insulating film made of a ferroelectric film, and a selection switching element including a MISFET having a gate insulating film made of a paraelectric film. A load element for a read operation is connected in series to the memory cell. The ferroelectric film and the paraelectric film are stacked with a semiconductor film being interposed therebetween. The semiconductor film forms a common channel shared by the MFSFET and the MISFET. The load element includes a MISFET having a channel made of the semiconductor film or a resistance element having a resistor made of the semiconductor film.

Abstract translation: 存储单元包括存储元件，其包括具有由铁电体膜构成的栅极绝缘膜的MFSFET，以及选择开关元件，其包括具有由绝缘膜形成的栅极绝缘膜的MISFET。 用于读取操作的负载元件与存储器单元串联连接。 铁电体膜和对称电介质膜层叠有半导体膜。 半导体膜形成由MFSFET和MISFET共享的公共通道。 负载元件包括具有由半导体膜形成的沟道的MISFET或具有由半导体膜制成的电阻器的电阻元件。

公开(公告)号：US20110309860A1

公开(公告)日：2011-12-22

申请号：US13222782

申请日：2011-08-31

Applicant: Yukihiro KANEKO

Inventor： Yukihiro KANEKO

IPC: H03K19/173

CPC classification number: H03K19/21 ,  G11C11/22 ,  H01L27/101 ,  H01L27/1159

Abstract: A non-volatile logic circuit includes a control electrode, a ferroelectric layer disposed on the control electrode, a semiconductor layer disposed on the ferroelectric layer, a power electrode and an output electrode disposed on the semiconductor layer, and first to fourth input electrodes disposed on the semiconductor layer. The first and second input electrodes receive first and second inputs, respectively. The third and fourth input electrodes receive inversion signals of the second and first input signal, respectively. A resistance value of the semiconductor layer between the power electrode and the output electrode varies according to the first input signal and the second input signal so that an exclusive-OR signal of the first and second input signals is output from the output electrode.

Abstract translation: 非易失性逻辑电路包括控制电极，设置在控制电极上的铁电层，设置在强电介质层上的半导体层，设置在半导体层上的电力电极和输出电极以及设置在半导体层上的第一至第四输入电极 半导体层。 第一和第二输入电极分别接收第一和第二输入。 第三和第四输入电极分别接收第二和第一输入信号的反相信号。 电源电极和输出电极之间的半导体层的电阻值根据第一输入信号和第二输入信号而变化，从而从输出电极输出第一和第二输入信号的异或信号。

公开(公告)号：US20110309858A1

公开(公告)日：2011-12-22

申请号：US13220222

申请日：2011-08-29

Applicant: Yukihiro KANEKO

Inventor： Yukihiro KANEKO

IPC: H03K19/185

CPC classification number: H01L27/10 ,  G11C11/22 ,  H01L27/101 ,  H01L27/11502

Abstract: In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The first input electrode is next to the second input electrode along the a direction orthogonal to the direction between the electric current source electrode and the output electrode. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first input electrode and the second input electrode, respectively, and a step of measuring current generated by applying the voltage between the electric current power electrode and the output electrode to determine on the basis of the current, which of the high or low resistant state the non-volatile logic circuit has.

Abstract translation: 在非易失性逻辑电路中，第一输入电极和第二输入电极形成在半导体层上并且在平面图中介于电流源电极和输出电极之间。 第一输入电极沿着与电流源电极和输出电极之间的方向正交的方向与第二输入电极相邻。 一种操作非易失性逻辑电路的方法包括分别通过向第一输入电极和第二输入电极施加电压来写入从四种状态中选出的一种状态的步骤，以及测量通过施加电压而产生的电流的步骤 电流功率电极和输出电极根据电流来确定非易失性逻辑电路具有哪些高或低电阻状态。

公开(公告)号：US20120217997A1

公开(公告)日：2012-08-30

申请号：US13465889

申请日：2012-05-07

Applicant: Yukihiro KANEKO

Inventor： Yukihiro KANEKO

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes.

公开(公告)号：US20120008365A1

公开(公告)日：2012-01-12

申请号：US13240225

申请日：2011-09-22

Applicant: Yukihiro KANEKO

Inventor： Yukihiro KANEKO

IPC: G11C11/22

CPC classification number: H01L27/10 ,  G11C11/22 ,  G11C11/5657 ,  H01L27/101 ,  H01L27/11502 ,  H01L29/7869

Abstract: A method of flowing a current selectively with a nonvolatile switching device according to the present disclosure includes a step of configuring, in the nonvolatile switching device, any one of a first state in which a current does not flow between the electrode group, a second state in which a current flows selectively between the first electrode and the second electrode, and a third state in which a current flows selectively between the first electrode and the third electrode. When any one of the first state, the second state and the third state is configured, voltages V1, Va, Vb and Vc, which satisfy predetermined inequality set corresponding to the one of the first to third states, are applied to the control electrode, the first electrode, the second electrode, and the third electrode, respectively.

Abstract translation: 根据本发明的一种使用非易失性开关器件选择性地流动电流的方法包括在非易失性开关器件中配置电流不在电极组之间的第一状态中的任何一种，第二状态 其中电流选择性地在第一电极和第二电极之间流动，并且电流在第一电极和第三电极之间选择性地流动的第三状态。 当配置第一状态，第二状态和第三状态中的任何一个时，满足对应于第一至第三状态之一的预定不等式的电压V1，Va，Vb和Vc被施加到控制电极， 第一电极，第二电极和第三电极。

公开(公告)号：US20110310650A1

公开(公告)日：2011-12-22

申请号：US13222658

申请日：2011-08-31

Applicant: Yukihiro KANEKO ,  Hiroyuki Tanaka ,  Michihito Ueda

Inventor： Yukihiro KANEKO ,  Hiroyuki Tanaka ,  Michihito Ueda

IPC: G11C11/22

CPC classification number: G11C11/22 ,  H01L27/1159 ,  H01L29/4908 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/78648

Abstract: In the operating method of the semiconductor memory device, (1) voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2>Vs, and V2>Vd, are applied to a first gate electrode, a second gate electrode, a source electrode, and a drain electrode to write a first resistance value, respectively, (2) the voltages V1, V2, Vs, and Vd, which satisfy V1>Vs, V1>Vd, V2

Abstract translation: 在半导体存储器件的操作方法中，（1）对第一栅电极施加满足V1> Vs，V1> Vd，V2> Vs，V2> Vd的电压V1，V2，Vs，Vd， 分别写入第一电阻值的第二栅电极，源电极和漏电极，（2）满足V1> Vs，V1> Vd，V2

公开(公告)号：US20130009713A1

公开(公告)日：2013-01-10

申请号：US13614498

申请日：2012-09-13

Applicant: Yu NISHITANI ,  Yukihiro KANEKO ,  Michihito UEDA

Inventor： Yu NISHITANI ,  Yukihiro KANEKO ,  Michihito UEDA

IPC: H03B5/24

CPC classification number: H03B5/20 ,  H01G7/06 ,  H01L23/64 ,  H01L25/16 ,  H01L28/20 ,  H01L28/40 ,  H01L28/55 ,  H01L28/56 ,  H01L2924/0002 ,  H03B5/24 ,  H03B2200/004 ,  H03B2201/02 ,  H03B2201/0208 ,  H01L2924/00

Abstract: A resistance-capacitance oscillation circuit comprises an amplifier and a phase shifting circuit. The phase shifting circuit comprises at least three resistance-capacitance circuit elements, which comprise a resistance and a capacitance. At least one of the resistance-capacitance circuit elements comprises a variable resistance and a variable capacitance. The variable resistance is formed of a first electrode, a second electrode, a part of a semiconductor film, a part of a ferroelectric film, and a fourth electrode. The variable capacitor is formed of the second electrode, a third electrode, a fifth electrode, another part of the ferroelectric film, another part of the semiconductor film, and a paraelectric film.

Abstract translation: 电阻 - 电容振荡电路包括放大器和移相电路。 相移电路包括至少三个电阻 - 电容电路元件，其包括电阻和电容。 电阻 - 电容电路元件中的至少一个包括可变电阻和可变电容。 可变电阻由第一电极，第二电极，半导体膜的一部分，铁电体膜的一部分和第四电极形成。 可变电容器由第二电极，第三电极，第五电极，铁电体膜的另一部分，半导体膜的另一部分和顺电膜形成。

公开(公告)号：US20120068732A1

公开(公告)日：2012-03-22

申请号：US13305075

申请日：2011-11-28

Applicant: Yukihiro KANEKO

Inventor： Yukihiro KANEKO

IPC: H03K19/173

CPC classification number: H03K19/173

Abstract: A nonvolatile logic circuit includes logic configuration electrodes and input electrodes. The nonvolatile logic circuit is programmable to any one of the logics between the input signals selected from logical conjunction (AND), logical disjunction (OR), logical non-conjunction (NAND), logical non-disjunction (NOR), and logical exclusive disjunction (XOR) by changing applied voltages to the logic configuration electrodes.

Abstract translation: 非易失性逻辑电路包括逻辑配置电极和输入电极。 非逻辑逻辑电路可编程为从逻辑连接（AND），逻辑分离（OR），逻辑非连接（NAND），逻辑非分离（NOR）和逻辑独占分离（NOR）之间选择的输入信号之间的任何逻辑电路 （XOR），通过将施加的电压改变为逻辑配置电极。