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公开(公告)号：US20220238155A1
公开(公告)日：2022-07-28
申请号：US17721985
申请日：2022-04-15
Inventor： Chien-An Lai , Chung-Cheng Chou , Yu-Der Chih
Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
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公开(公告)号：US10991426B2
公开(公告)日：2021-04-27
申请号：US16694114
申请日：2019-11-25
Inventor： Chung-Cheng Chou , Tien-Yen Wang
IPC: G11C13/00
Abstract: A memory device includes a memory array including a plurality of memory cells arranged in rows and columns. A closed loop bias generator is configured to output a column select signal to the memory array. A current limiter receives an output of the closed loop bias generator. The current limiter is coupled to a plurality of the columns of the memory array.
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公开(公告)号：US10930344B2
公开(公告)日：2021-02-23
申请号：US16422924
申请日：2019-05-24
Inventor： Chung-Cheng Chou , Hsu-Shun Chen , Chien-An Lai , Pei-Ling Tseng , Zheng-Jun Lin
IPC: G11C13/00
Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.
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公开(公告)号：US20200020397A1
公开(公告)日：2020-01-16
申请号：US16502671
申请日：2019-07-03
Inventor： Chien-An Lai , Chung-Cheng Chou , Yu-Der Chih
Abstract: A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.
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Patent Agency Ranking
公开(公告)号：US09472245B2
公开(公告)日：2016-10-18
申请号：US14145700
申请日：2013-12-31
Inventor： Po-Hao Lee , Chung-Cheng Chou
CPC classification number: G11C7/06 , G11C7/065 , G11C11/1673 , G11C13/004 , G11C2013/0054
Abstract: A device includes first and second current mirrors electrically connected to reference and cell current sources of a memory array. A first inverter is electrically connected to the first current mirror, and a second inverter is electrically connected to the second current mirror. The first and second inverters are cross-coupled.
Abstract translation: 一种器件包括电连接到存储器阵列的参考和电池电流源的第一和第二电流镜。 第一逆变器电连接到第一电流镜，第二反相器电连接到第二电流镜。 第一和第二逆变器是交叉耦合的。
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公开(公告)号：US20160224039A1
公开(公告)日：2016-08-04
申请号：US15093211
申请日：2016-04-07
Inventor： Chung-Cheng Chou , Po-Hao Lee
CPC classification number: G05F1/468 , G05F1/46 , G05F1/575 , H02M1/12 , H02M3/3382
Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.
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公开(公告)号：US09397624B2
公开(公告)日：2016-07-19
申请号：US14329866
申请日：2014-07-11
Inventor： Chung-Cheng Chou
CPC classification number: H03F3/505 , H03F3/45183 , H03F2200/135 , H03F2200/456 , H03F2200/555 , H03F2203/45674
Abstract: A device includes an amplifier stage, a source follower, a resistive device, and a transistor. The source follower has an input terminal electrically coupled to an internal node of the amplifier stage, and an output terminal electrically coupled to an input terminal of the amplifier stage and an output terminal of the device. The resistive device has a first terminal electrically coupled to the output terminal of the device. The transistor is electrically coupled to a second terminal of the resistive device and the amplifier stage.
Abstract translation: 器件包括放大器级，源极跟随器，电阻器件和晶体管。 源极跟随器具有电耦合到放大器级的内部节点的输入端子和电耦合到放大器级的输入端子和该器件的输出端子的输出端子。 电阻器件具有电耦合到器件的输出端子的第一端子。 晶体管电耦合到电阻器件和放大器级的第二端子。
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78.发明申请Resistive Random Access Memory (RRAM) with Improved Forming Voltage Characteristics and Method for Making 有权具有改进的成形电压特性的电阻随机存取存储器（RRAM）和制造方法公开(公告)号：US20150137059A1
公开(公告)日：2015-05-21
申请号：US14081916
申请日：2013-11-15
Inventor： Jonathan Tehan Chen , Chung-Cheng Chou , Po-Hao Lee , Kuo-Chi Tu
CPC classification number: H01L45/1253 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: The present disclosure provides resistive random access memory (RRAM) structures and methods of making the same. The RRAM structures include a bottom electrode having protruded step portion that allows formation of a self-aligned conductive path with a top electrode during operation. The protruded step portion may have an inclination angle of about 30 degrees to 150 degrees. Multiple RRAM structures may be formed by etching through a RRAM stack.
Abstract translation: 本公开提供了电阻随机存取存储器（RRAM）结构及其制造方法。 RRAM结构包括具有突出台阶部分的底部电极，其允许在操作期间与顶部电极形成自对准导电路径。 突出台阶部分可以具有约30度至150度的倾斜角度。 可以通过通过RRAM堆叠进行蚀刻来形成多个RRAM结构。
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公开(公告)号：US20150130427A1
公开(公告)日：2015-05-14
申请号：US14080238
申请日：2013-11-14
Inventor： Chung-Cheng Chou , Po-Hao Lee
IPC: G05F1/46
CPC classification number: G05F1/468 , G05F1/46 , G05F1/575 , H02M1/12 , H02M3/3382
Abstract: A device is configured to provide low dropout regulation. An amplifier stage includes a first transistor electrically connected to an output of the device, and a second transistor. A current mirror includes a third transistor electrically connected to the second transistor, and a fourth transistor electrically connected to the third transistor. The auxiliary current source has a control terminal electrically connected to a gate electrode of the fourth transistor. The pull down stage includes a fifth transistor having a gate electrode electrically connected to a drain electrode of the first transistor, and a sixth transistor having a gate electrode electrically connected to the gate electrode of the fourth transistor. The pull up transistor has a gate electrode electrically connected to a drain electrode of the fifth transistor. The first capacitor has a first terminal electrically connected to the gate electrode of the first transistor.
Abstract translation: 一种设备被配置为提供低压差调节。 放大器级包括电连接到器件的输出的第一晶体管和第二晶体管。 电流镜包括电连接到第二晶体管的第三晶体管和与第三晶体管电连接的第四晶体管。 辅助电流源具有电连接到第四晶体管的栅电极的控制端子。 下拉级包括具有电连接到第一晶体管的漏电极的栅电极的第五晶体管和与第四晶体管的栅电极电连接的栅电极的第六晶体管。 上拉晶体管具有电连接到第五晶体管的漏电极的栅电极。 第一电容器具有电连接到第一晶体管的栅电极的第一端子。
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