公开(公告)号：US20200118516A1

公开(公告)日：2020-04-16

申请号：US16243968

申请日：2019-01-09

Applicant: Samsung Display Co., Ltd.

Inventor： Kyunglok Kim ,  Amir Amirkhany

IPC: G09G5/00

Abstract: Provided is a method of reducing power consumption by a display device including an encoder for receiving a stream of data, and for compressing the data, a TX rate-buffer for receiving and storing the compressed data, a PHY for receiving the compressed data, a RX rate-buffer for receiving and storing the compressed data, and a decoder for receiving the compressed data, and for decompressing the compressed data to reconstruct original data, the method including placing the PHY a SLEEP state to reduce power consumption of the PHY when the TX rate-buffer transmits a last bit of the compressed data in the TX rate-buffer to the PHY, and placing the PHY in a TRANSMIT/ACTIVE state when a fullness of the TX rate-buffer reaches a reference threshold, or a last bit of compressed data corresponding to a last pixel of a line of pixels is placed in the TX rate-buffer.

公开(公告)号：US20200074957A1

公开(公告)日：2020-03-05

申请号：US16183488

申请日：2018-11-07

Applicant: Samsung Display Co., Ltd.

Inventor： Amir Amirkhany ,  Charlene Ku

IPC: G09G5/00 ,  G06F1/32 ,  G06F1/10

Abstract: Provided is a method of reducing power consumption by a display device including a display logic for processing pixel data, and a display panel including a plurality of pixels, the method including receiving the pixel data corresponding to the plurality of pixels, determining whether a number of consecutive pixels of the plurality of pixels that correspond to identical data of the pixel data reaches a threshold number, and powering down the display logic when the number of consecutive pixels exceeds the threshold number.

公开(公告)号：US20190287480A1

公开(公告)日：2019-09-19

申请号：US16271542

申请日：2019-02-08

Applicant: Samsung Display Co., Ltd.

Inventor： Amir Amirkhany

IPC: G09G5/00

Abstract: A scalable driving architecture for large size display includes a display; a low voltage integrated circuit configured to: receive a high-speed input signal; process the input signal; and output uncompressed pixel data based on the processed input signal; and a first high voltage integrated circuit configured to drive pixels in the display based on the uncompressed pixel data; wherein the low voltage integrated circuit is configured to provide the uncompressed pixel data to the first high voltage integrated circuit via a first low-to-high (L2H) interface, and wherein the low voltage integrated circuit and the first high voltage integrated circuit are assembled on a film.

公开(公告)号：US20190287479A1

公开(公告)日：2019-09-19

申请号：US16271511

申请日：2019-02-08

Applicant: Samsung Display Co., Ltd.

Inventor： Amir Amirkhany

IPC: G09G5/00 ,  G09G5/04

Abstract: A low power architecture for mobile displays includes a display, a low voltage integrated circuit configured to: receive a high speed input signal; process the input signal; and output uncompressed pixel data based on the processed input signal; and a high voltage integrated circuit configured to drive pixels in the display based on the uncompressed pixel data; wherein the low voltage integrated circuit is configured to provides the uncompressed pixel data to the high voltage integrated circuit via a timing-to-driver (T2D) interface.

公开(公告)号：US10140912B2

公开(公告)日：2018-11-27

申请号：US14974535

申请日：2015-12-18

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Mohammad Hekmat ,  Amir Amirkhany

IPC: G09G3/20

Abstract: A display interface for transmitting reverse data. The display interface includes a timing controller, a first plurality of driver integrated circuits, a first shared data lane connected to the timing controller and to each of the first plurality of driver integrated circuits, and a shared synchronization lane connected to the timing controller and to each of the first plurality of driver integrated circuits. Each of the first plurality of driver integrated circuits has a data input configured to receive reverse data from a display panel, and a buffer configured to store reverse data. The timing controller is configured to periodically send a synchronization pulse having a triggering edge. Each of the first plurality of driver integrated circuits is configured to periodically send, on the first shared data lane, reverse data to the timing controller in a respective time slot of a plurality of non-overlapping time slots, after each triggering edge.

公开(公告)号：US20180013434A1

公开(公告)日：2018-01-11

申请号：US15256444

申请日：2016-09-02

Applicant: Samsung Display Co., Ltd.

Inventor： Amir Amirkhany ,  Ashkan Roshan Zamir

IPC: H03L7/08 ,  H03L7/099 ,  H03L7/093 ,  H04L12/801 ,  H03L7/089

CPC classification number: H03L7/0807 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/099 ,  H03L7/101 ,  H04L47/29

Abstract: A system and method for correcting for phase errors, in a phase locked loop, resulting from spread spectrum clocking involving a reference clock signal having a frequency modulation. A correction generation circuit generates an offset signal, that when injected after the charge pump of the phase locked loop, causes the voltage controlled oscillator to produce a signal with substantially the same frequency modulation, thereby reducing the phase error. The correction generation circuit may include a timing estimation circuit for estimating the times at which transitions (between positive-sloping and negative-sloping portions of the triangle wave) occur, and an amplitude estimation circuit for estimating the amplitude of the offset signal that results in a reduction in the phase error.

公开(公告)号：US09805693B2

公开(公告)日：2017-10-31

申请号：US14951387

申请日：2015-11-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Amir Amirkhany ,  Sanquan Song

IPC: G09G5/00 ,  G09G5/18

CPC classification number: G09G5/18 ,  G09G2330/026 ,  G09G2360/04 ,  G09G2370/04 ,  G09G2370/08

Abstract: A chain of bidirectional display driver integrated circuits (DICs). The chain has a beginning and an end, the chain includes a plurality of DICs, each of the plurality of DICs including: a direct data input, a relay data input, and a relay data output. Each of the plurality of DICs is configured to combine data received at the direct data input with a stream of bits received at the relay data input to form combined data, and to transmit the combined data through the relay data output.

公开(公告)号：US09680430B2

公开(公告)日：2017-06-13

申请号：US14061637

申请日：2013-10-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Mohammad Hekmat ,  Amir Amirkhany

IPC: H03F3/45 ,  H03K5/08 ,  H04L25/49

CPC classification number: H03F3/45179 ,  H03F3/45183 ,  H03K5/082 ,  H04L25/4917

Abstract: A differential amplifier including: a first amplifier leg including a first transistor, and a second amplifier leg including a second transistor. Here, the first transistor is configured to have a bulk potential different from a bulk potential of the second transistor. The first amplifier leg and the second amplifier leg, together, may be configured to differentially amplify a received differential input signal. The differential amplifier may be configured to have an input offset voltage, which corresponds to the difference between the bulk potential of the first transistor and the bulk potential of the second transistor. The differential amplifier may be at an input stage of a comparator.

公开(公告)号：US09595975B1

公开(公告)日：2017-03-14

申请号：US15144521

申请日：2016-05-02

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sanquan Song ,  Amir Amirkhany

IPC: H03H7/40 ,  H03M1/12 ,  H03K19/0944

CPC classification number: H03M1/12 ,  H03K19/0944

Abstract: A low-latency, high-gain (LLHG) slicer includes an input stage coupled to a differential output port and configured to receive a differential analog input signal, and to track the differential analog input signal during a tracking phase, an output stage coupled to the differential output port and configured to generate digital output bits corresponding to the differential analog input signal during a regeneration phase, and a tunable resistor coupled to the differential output port and configured to provide a first load impedance during the tracking phase and to provide a second load impedance during the regeneration phase, the first load impedance being lower than the second load impedance.

Abstract translation: 低延迟高增益（LLHG）限幅器包括耦合到差分输出端口并被配置为接收差分模拟输入信号的输入级，并且在跟踪阶段跟踪差分模拟输入信号，耦合到 所述差分输出端口并且被配置为在再生阶段期间产生与所述差分模拟输入信号相对应的数字输出位，以及耦合到所述差分输出端口并被配置为在所述跟踪阶段期间提供第一负载阻抗并且提供第二 在再生阶段期间的负载阻抗，第一负载阻抗低于第二负载阻抗。

公开(公告)号：US09413339B2

公开(公告)日：2016-08-09

申请号：US14290894

申请日：2014-05-29

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Amir Amirkhany ,  Mohammad Hekmat

IPC: H03L7/06 ,  H03K3/017 ,  H03K5/156

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: An electronic device includes a clock configured to transmit a first clock signal and a second clock signal for operation of the electronic device; a duty cycle corrector coupled to the clock to correct a duty cycle of the first and second clock signals, the duty cycle corrector being configured to: assign and store a first duty cycle correction code in response to the first clock signal; assign and store a second duty cycle correction code in response to the second clock signal; calculate an offset code based on the first and second duty cycle correction codes; and negate the offset code from results of duty cycle correction operations.

Abstract translation: 电子设备包括被配置为发送第一时钟信号的时钟和用于电子设备的操作的第二时钟信号; 负载周期校正器，耦合到时钟以校正第一和第二时钟信号的占空比，占空比校正器被配置为：响应于第一时钟信号分配和存储第一占空比校正码; 分配和存储响应于第二时钟信号的第二占空比校正码; 基于第一和第二占空比校正码计算偏移码; 并且将偏移代码与占空比校正操作的结果否定。