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83 条记录 (耗时 0.031 秒)

    Integrated circuit arrangement comprising isolating trenches and a field effect transistor
    73.
    发明授权
    Integrated circuit arrangement comprising isolating trenches and a field effect transistor 有权
    集成电路装置，包括隔离沟槽和场效应晶体管

    公开(公告)号：US07880264B2

    公开(公告)日：2011-02-01

    申请号：US11273618

    申请日：2005-11-14

    申请人： Ronald Kakoschke ,  Franz Schuler

    发明人： Ronald Kakoschke ,  Franz Schuler

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

    摘要： A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.

    摘要翻译： 公开了一种存储器电路装置和制造方法。 存储器电路装置具有存储单元区域。 存储单元区域包含存储单元晶体管，其一列使用三栅极区域选择晶体管来选择。 晶体管具有延伸到隔离沟槽中的栅极区域。 隔离沟槽隔离存储单元阵列的不同列中的存储单元。

    Bit line structure and method for the production thereof
    74.
    发明授权
    Bit line structure and method for the production thereof 有权
    位线结构及其制造方法

    公开(公告)号：US07687842B2

    公开(公告)日：2010-03-30

    申请号：US11273595

    申请日：2005-11-14

    申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L27/108

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

    摘要： A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

    摘要翻译： 为半导体元件或电路布置提供了位线结构和相关联的制造方法。 位线结构包含表面位线和掩埋位线。 掩埋位线形成在沟槽的上部，并且经由第一连接层连接到相关联的第一掺杂区域。 通过第二沟槽绝缘层与掩埋位线绝缘的第一沟槽填充层位于沟槽的下部。

    Memory circuit arrangement with a cell array substrate and a logic circuit substrate and method for the production thereof
    77.
    发明授权
    Memory circuit arrangement with a cell array substrate and a logic circuit substrate and method for the production thereof 有权
    具有单元阵列基板和逻辑电路基板的存储器电路布置及其制造方法

    公开(公告)号：US07460385B2

    公开(公告)日：2008-12-02

    申请号：US11251355

    申请日：2005-10-14

    申请人： Wolfgang Gruber ,  Ronald Kakoschke ,  Thomas Schweizer ,  Dominik Wegertseder

    发明人： Wolfgang Gruber ,  Ronald Kakoschke ,  Thomas Schweizer ,  Dominik Wegertseder

    IPC分类号： G11C5/02 ,  G11C5/06

    CPC分类号： G11C5/025 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a memory circuit arrangement and fabrication method, the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.

    摘要翻译： 在存储器电路布置和制造方法中，存储器电路装置的部分位于两个不同的衬底上。 集成存储单元阵列位于一个衬底上。 控制对存储单元的访问的集成控制电路位于另一（逻辑电路）基板上。 当读取，写入或擦除存储单元的内容时，控制电路控制序列。 逻辑电路基板还包含CPU和加密协处理器。 存储器电路包括读出放大器，借助于此可以确定存储器单元的存储状态，以及选择字或位线的解码电路。

    Bit line structure and method of fabrication
    79.
    发明申请
    Bit line structure and method of fabrication 有权
    位线结构和制造方法

    公开(公告)号：US20070049050A1

    公开(公告)日：2007-03-01

    申请号：US11592844

    申请日：2006-11-02

    申请人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

    发明人： Ronald Kakoschke ,  Danny Shum ,  Georg Tempel

    IPC分类号： H01L21/31

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/66833

    摘要： The invention relates to a bit line structure having a surface bit line (DLx) and a buried bit line (SLx), the buried bit line (SLx) being formed in a trench with a trench insulation layer (6) and being connected to doping regions (10) with which contact is to be made via a covering connecting layer (12) and a self-aligning terminal layer (13) in an upper partial region of the trench.

    摘要翻译： 本发明涉及一种具有表面位线（DLx）和掩埋位线（SLx）的位线结构，埋入位线（SLx）形成在具有沟槽绝缘层（6）的沟槽中，并与掺杂 通过覆盖连接层（12）和沟槽的上部部分区域中的自对准端子层（13）与其接触的区域（10）。