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公开(公告)号:US20190273921A1
公开(公告)日:2019-09-05
申请号:US16287252
申请日:2019-02-27
Inventor: Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA , Ryuichi KANOH , Chong Soon LIM , Ru Ling LIAO , Hai Wei SUN , Sughosh Pavan SHASHIDHAR , Han Boon TEO , Jing Ya LI
IPC: H04N19/119 , H04N19/46 , H04N19/107 , H04N19/176
Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: writes, into a bitstream, one or more parameters including a first parameter indicating that a first partition of an image is to be split into a plurality of partitions including at least a second partition which is a non-rectangular partition; splits the first partition, based on the first parameter; and encodes at least the second partition.
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公开(公告)号:US20190191167A1
公开(公告)日:2019-06-20
申请号:US16222104
申请日:2018-12-17
Inventor: Virginie DRUGEON , Tadamasa TOMA , Takahiro NISHI , Kiyofumi ABE , Ryuichi KANOH
IPC: H04N19/132 , H04N19/159 , H04N19/117 , H04N19/196 , H04N19/182
CPC classification number: H04N19/132 , H04N19/117 , H04N19/159 , H04N19/182 , H04N19/198
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry performs: deriving a plurality of reference samples positioned on a first line, for intra prediction; and generating a prediction image using the plurality of reference samples. The deriving includes interpolating a value on a second line perpendicular to the first line using values of encoded pixels on the second line to generate an interpolated value, and deriving one of the plurality of reference samples by projecting the interpolated value onto the first line.
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公开(公告)号:US20190089958A1
公开(公告)日:2019-03-21
申请号:US16192070
申请日:2018-11-15
Inventor: Takahiro NISHI , Tadamasa TOMA , Kiyofumi ABE
IPC: H04N19/13 , H04N19/159 , H04N19/174 , H04N19/172 , H04N19/124
Abstract: An encoder is an encoder which encodes image information and includes memory and circuitry accessible to the memory. The circuitry derives, from the image information, a binary data string according to binarization for arithmetic encoding, and outputs a bit stream including the binary data string and application information indicating whether or not the binary data string has been arithmetic encoded. The circuitry outputs, as the bit stream, a string including as the binary data string, a data string which has not been arithmetic encoded; and, as the application information, information indicating that the binary data string has not been arithmetic encoded.
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公开(公告)号:US20170302956A1
公开(公告)日:2017-10-19
申请号:US15640824
申请日:2017-07-03
Inventor: Satoshi KONDO , Shinya KADONO , Makoto HAGAI , Kiyofumi ABE
IPC: H04N19/52 , H04N19/103 , H04N19/583 , H04N19/58 , H04N19/577 , H04N19/573 , H04N19/513 , H04N19/51 , H04N19/46 , H04N19/423 , H04N19/30 , H04N19/61 , H04N19/176 , H04N19/172 , H04N19/16 , H04N19/159 , H04N19/137 , H04N19/136 , H04N19/127 , H04N19/107 , H04N19/105 , H04N19/70 , H04N19/184
CPC classification number: H04N19/52 , H04N19/103 , H04N19/105 , H04N19/107 , H04N19/127 , H04N19/136 , H04N19/137 , H04N19/159 , H04N19/16 , H04N19/172 , H04N19/176 , H04N19/184 , H04N19/30 , H04N19/423 , H04N19/46 , H04N19/51 , H04N19/513 , H04N19/573 , H04N19/577 , H04N19/58 , H04N19/583 , H04N19/61 , H04N19/70
Abstract: When a block (MB22) of which motion vector is referred to in the direct mode contains a plurality of motion vectors, 2 motion vectors MV23 and MV24, which are used for inter picture prediction of a current picture (P23) to be coded, are determined by scaling a value obtained from averaging the plurality of motion vectors or selecting one of the plurality of the motion vectors.
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公开(公告)号:US20150373363A1
公开(公告)日:2015-12-24
申请号:US14840427
申请日:2015-08-31
Inventor: Satoshi KONDO , Shinya KADONO , Makoto HAGAI , Kiyofumi ABE
IPC: H04N19/52 , H04N19/105 , H04N19/184 , H04N19/176 , H04N19/172
CPC classification number: H04N19/52 , H04N19/105 , H04N19/137 , H04N19/139 , H04N19/172 , H04N19/176 , H04N19/184 , H04N19/50 , H04N19/51 , H04N19/513 , H04N19/517 , H04N19/521 , H04N19/533 , H04N19/537 , H04N19/56 , H04N19/577 , H04N19/593 , H04N19/61
Abstract: A motion vector coding unit executes processing including a neighboring block specification step of specifying a neighboring block which is located in the neighborhood of a current block; a judgment step of judging whether or not the neighboring block has been coded using a motion vector of another block; a prediction step of deriving a predictive motion vector of the current block using a motion vector calculated from the motion vector of the other block as a motion vector of the neighboring block; and a coding step of coding the motion vector of the current block using the predictive motion vector.
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76.
公开(公告)号:US20150110196A1
公开(公告)日:2015-04-23
申请号:US14584407
申请日:2014-12-29
Inventor: Shinya KADONO , Satoshi KONDO , Makoto HAGAI , Kiyofumi ABE
IPC: H04N19/513
CPC classification number: H04N19/52 , G06F1/03 , G06F2101/12 , H04N19/105 , H04N19/124 , H04N19/172 , H04N19/176 , H04N19/30 , H04N19/43 , H04N19/503 , H04N19/51 , H04N19/513 , H04N19/577 , H04N19/587 , H04N19/61 , H04N19/625 , H04N21/2743
Abstract: A motion vector derivation unit includes a comparison unit for comparing a parameter TR1 for a reference vector with a predetermined value to determine whether it exceeds the predetermined value or not; a switching unit for switching selection between the maximum value of a pre-stored parameter TR and the parameter TR1 according to the comparison result by the comparison unit; a multiplier parameter table (for multipliers); and a multiplier parameter table (for divisors) for associating the parameter TR1 with a value approximate to the inverse value (1/TR1) of this parameter TR1.
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公开(公告)号:US20150055713A1
公开(公告)日:2015-02-26
申请号:US14532284
申请日:2014-11-04
Inventor: Satoshi KONDO , Shinya KADONO , Makoto HAGAI , Kiyofumi ABE
IPC: H04N19/513 , H04N19/176
CPC classification number: H04N19/52 , H04N19/105 , H04N19/137 , H04N19/139 , H04N19/172 , H04N19/176 , H04N19/184 , H04N19/50 , H04N19/51 , H04N19/513 , H04N19/517 , H04N19/521 , H04N19/533 , H04N19/537 , H04N19/56 , H04N19/577 , H04N19/593 , H04N19/61
Abstract: A motion vector coding unit executes processing including a neighboring block specification step of specifying a neighboring block which is located in the neighborhood of a current block; a judgment step of judging whether or not the neighboring block has been coded using a motion vector of another block; a prediction step of deriving a predictive motion vector of the current block using a motion vector calculated from the motion vector of the other block as a motion vector of the neighboring block; and a coding step of coding the motion vector of the current block using the predictive motion vector.
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公开(公告)号:US20250106418A1
公开(公告)日:2025-03-27
申请号:US18976551
申请日:2024-12-11
Inventor: Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC: H04N19/423 , H04N19/105 , H04N19/176 , H04N19/517
Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry performs prediction on an image. A motion vector predictor list used in the prediction includes a spatially neighboring motion vector predictor obtained from a block spatially neighboring a current block, and a spatially broad motion vector predictor obtained from a block positioned at any of a plurality of predetermined positions in a second range that is broader than a first range that spatially neighbors the current block. The plurality of predetermined positions are defined by a regular interval using the top-left of a current picture as a reference point.
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公开(公告)号:US20250106417A1
公开(公告)日:2025-03-27
申请号:US18976662
申请日:2024-12-11
Inventor: Han Boon TEO , Jingying GAO , Chong Soon LIM , Praveen Kumar YADAV , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC: H04N19/42 , H04N19/117 , H04N19/136 , H04N19/172
Abstract: A decoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: decodes a plurality of sets of neural network information each of which identifies a neural network filter; decodes, from one access unit, two or more sets of activation information each of which specifies one set of neural network information among the plurality of sets of neural network information; and applies, to one picture, two or more neural network filters identified by two or more sets of neural network information specified by the two or more sets of activation information.
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公开(公告)号:US20250024021A1
公开(公告)日:2025-01-16
申请号:US18899768
申请日:2024-09-27
Inventor: Ru Ling LIAO , Chong Soon LIM , Hai Wei SUN , Han Boon TEO , Jing Ya LI , Sughosh Pavan SHASHIDHAR , Kiyofumi ABE , Takahiro NISHI , Tadamasa TOMA
IPC: H04N19/105 , H04N19/159 , H04N19/176 , H04N19/46
Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. The circuitry, in operation, stores a first parameter into a bitstream, the first parameter indicating, as a prediction mode, one of (i) a multiple prediction mode in which a prediction image is generated by overlapping an inter prediction image of a current block and an intra prediction image of the current block and (ii) one of a plurality of prediction modes including a non-rectangular mode in which a prediction image is generated for each non-rectangular partition in the current block, and encodes the current block according to the prediction mode.
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