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    Non-linear polar material based differential multi-memory element gain bit-cell
    75.
    发明授权
    Non-linear polar material based differential multi-memory element gain bit-cell 有权

    公开(公告)号：US11514967B1

    公开(公告)日：2022-11-29

    申请号：US17367217

    申请日：2021-07-02

    Applicant: Kepler Computing Inc.

    Inventor： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

    IPC: G11C11/22 ,  G11C11/417

    Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

    Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell
    76.
    发明授权
    Method of forming stacked ferroelectric non- planar capacitors in a memory bit-cell 有权

    公开(公告)号：US11501813B1

    公开(公告)日：2022-11-15

    申请号：US17390791

    申请日：2021-07-30

    Applicant: Kepler Computing Inc.

    Inventor： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

    IPC: G11C11/22 ,  G11C11/417

    Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

    Stacked ferroelectric non-planar capacitors in a memory bit-cell
    77.
    发明授权
    Stacked ferroelectric non-planar capacitors in a memory bit-cell 有权

    公开(公告)号：US11423967B1

    公开(公告)日：2022-08-23

    申请号：US17359311

    申请日：2021-06-25

    Applicant: Kepler Computing Inc.

    Inventor： Rajeev Kumar Dokania ,  Noriyuki Sato ,  Tanay Gosavi ,  Pratyush Pandey ,  Debo Olaosebikan ,  Amrita Mathuriya ,  Sasikanth Manipatruni

    IPC: G11C11/22 ,  G11C11/417

    Abstract: A high-density low voltage ferroelectric (or paraelectric) memory bit-cell that includes a planar ferroelectric or paraelectric capacitor. The memory bit-cell comprises 1T1C configuration, where a plate-line is parallel to a word-line, or the plate-line is parallel to a bit-line. The memory bit-cell can be 1TnC, where ‘n’ is a number. In a 1TnC bit-cell, the capacitors are vertically stacked allowing for multiple values to be stored in a single bit-cell. The memory bit-cell can be multi-element FE gain bit-cell. In a multi-element FE gain bit-cell, data sensing is done with signal amplified by a gain transistor in the bit-cell. As such, higher storage density is realized using multi-element FE gain bit-cells. In some examples, the 1T1C, 1TnC, and multi-element FE gain bit-cells are multi-level bit-cells. To realize multi-level bit-cells, the capacitor is placed in a partially switched polarization state by applying different voltage levels or different time pulse widths at the same voltage level.

    Embedded memory adjacent to non-memory
    78.
    发明授权
    Embedded memory adjacent to non-memory 有权

    公开(公告)号：US12238935B1

    公开(公告)日：2025-02-25

    申请号：US18360764

    申请日：2023-07-27

    Applicant: Kepler Computing Inc.

    Inventor： Noriyuki Sato ,  Tanay Gosavi ,  Niloy Mukherjee ,  Rajeev Kumar Dokania ,  Amrita Mathuriya ,  Sasikanth Manipatruni

    IPC: H10B53/40

    Abstract: A process integration and patterning flow used to pattern a memory array area for an embedded memory without perturbing a fabricating process for logic circuitries. The fabrication process uses a pocket mask (e.g., a hard mask) to decouple the etching process of a memory array area and non-memory area. Such decoupling allows for a simpler fabrication process with little to no impact on the current fabrication process. The fabrication process may use multiple pocket masks to decouple the etching process of the memory array area and the non-memory area. This fabrication process (using multiple pocket masks) allows to avoid exposure of memory material into a second pocket etch chamber. The process of etching memory material is decoupled from the process of etching an encapsulation material. Examples of embedded memory include dynamic random-access memory and ferroelectric random-access memory.

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