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公开(公告)号:US10679119B2
公开(公告)日:2020-06-09
申请号:US15468838
申请日:2017-03-24
Applicant: INTEL CORPORATION
Inventor: Arnab Paul , Narayan Srinivasa
IPC: G06N3/04
Abstract: The present disclosure provides for generating a spiking neural network. Generating a spiking neural network can include determining that a first input fan-in from a plurality of input neurons to each of a plurality of output neurons is greater than a threshold, generating a plurality of intermediate neurons based on a determination that the first input fan-in is greater than the threshold, and coupling the plurality of intermediate neurons to the plurality of input neurons and the plurality of output neurons, wherein each of the plurality of intermediate neurons has a second input fan-in that is less than the first input fan-in and each of the plurality of output neurons has a third input fan-in that is less than the first input fan-in.
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公开(公告)号:US10521349B2
公开(公告)日:2019-12-31
申请号:US16277267
申请日:2019-02-15
Applicant: Intel Corporation
Inventor: Chandrasekaran Sakthivel , Prasoonkumar Surti , John C. Weast , Sara S. Baghsorkhi , Justin E. Gottschlich , Abhishek R. Appu , Nicolas C. Galoppo Von Borries , Joydeep Ray , Narayan Srinivasa , Feng Chen , Ben J. Ashbaugh , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha , Eriko Nurvitadhi , Balaji Vembu , Altug Koker
IPC: G06F12/0837 , G06N3/08 , G06N20/00 , G06T1/20 , G06F12/0815 , G06N3/04 , G06N3/063
Abstract: In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit cores, and a machine learning model communicatively coupled to the plurality of processing unit cores, wherein the plurality of cache memory modules share cache coherency data with the machine learning model. Other embodiments are also disclosed and claimed.
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73.
公开(公告)号:US20190139182A1
公开(公告)日:2019-05-09
申请号:US16197783
申请日:2018-11-21
Applicant: Intel Corporation
Inventor: Eriko Nurvitadhi , Balaji Vembu , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Kamal Sinha , Nadathur Rajagopalan Satish , Jeremy Bottleson , Farshad Akhbari , Altug Koker , Narayan Srinivasa , Dukhwan Kim , Sara S. Baghsorkhi , Justin E. Gottschlich , Feng Chen , Elmoustapha Ould-Ahmed-Vall , Kevin Nealis , Xiaoming Chen , Anbang Yao
CPC classification number: G06T1/20 , G06F9/3001 , G06F9/3017 , G06F9/3851 , G06F9/3887 , G06F9/3895 , G06N3/04 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N3/084
Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex machine learning compute operation.
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公开(公告)号:US20180308208A1
公开(公告)日:2018-10-25
申请号:US15819093
申请日:2017-11-21
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
CPC classification number: G06T1/20 , G06F8/41 , G06F9/45533 , G06F9/5061 , G06F9/5094 , G06F17/16 , G06F2009/45583 , G06T1/60
Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type
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公开(公告)号:US20180307971A1
公开(公告)日:2018-10-25
申请号:US15495020
申请日:2017-04-24
Applicant: Intel Corporation
Inventor: Kamal Sinha , Balaji Vembu , Eriko Nurvitadhi , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Farshad Akhbari , Narayan Srinivasa , Feng Chen , Dukhwan Kim , Nadathur Rajagopalan Satish , John C. Weast , Mike B. MacPherson , Linda L. Hurd , Vasanth Ranganathan , Sanjeev S. Jahagirdar
CPC classification number: G06N3/063 , G06F1/3287 , G06F1/3293 , G06F9/30014 , G06F9/30036 , G06F15/78 , G06N3/04 , G06N3/08 , G06T1/20 , G06T1/60 , G06T15/005
Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.
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公开(公告)号:US20180293205A1
公开(公告)日:2018-10-11
申请号:US15482796
申请日:2017-04-09
Applicant: Intel Corporation
Inventor: Altug Koker , Farshad Akhbari , Feng Chen , Dukhwan Kim , Narayan Srinivasa , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Joydeep Ray , Ping T. Tang , Michael Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu
CPC classification number: G06F15/8007 , G06F9/3004 , G06F13/00 , G06F13/4027 , G06N3/0445 , G06N3/0454 , G06N3/0481 , G06N3/063 , G06N3/084 , G06T1/20
Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.
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公开(公告)号:US20180276530A1
公开(公告)日:2018-09-27
申请号:US15468881
申请日:2017-03-24
Applicant: INTEL CORPORATION
Inventor: Arnab Paul , Narayan Srinivasa
Abstract: Embodiments described herein describe object recognition using a spiking neural network. Object recognition using a spiking neural network can include processing each of the plurality of base templates through a plurality of input neurons to generate a plurality of first spikes through the plurality of input neurons, providing the plurality of first spikes from the plurality of input neurons to each of a plurality of excitatory neurons (E-neurons), providing a plurality of second spikes from a plurality of inhibitory neurons (I-neurons) to the plurality of E-neurons to inhibit a spiking rate of the E-neurons, generating a plurality of weights at each of the plurality of E-neurons based on the plurality of first spikes and the plurality of second spikes, and classifying a pattern utilizing the plurality of input neurons, the plurality of E-neurons, and the plurality of weights at each of the E-neurons.
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公开(公告)号:US20180174042A1
公开(公告)日:2018-06-21
申请号:US15385334
申请日:2016-12-20
Applicant: Intel Corporation
Inventor: Narayan Srinivasa , Yongqiang Cao , Andreas Wild
CPC classification number: G06N3/08 , G06N3/0454 , G06N3/049
Abstract: Systems and methods for supervised learning and cascaded training of a neural network are described. In an example, a supervised process is used for strengthening connections to classifier neurons, with a supervised learning process of receiving a first spike at a classifier neuron from a processing neuron in response to training data, and receiving an out-of-band communication of a second desired (artificial) spike at the classifier neuron that corresponds to the classification of the training data. As a result of spike timing dependent plasticity, connections to the classifier neuron are strengthened. In another example, a cascaded technique is disclosed to generate a plurality of trained neural networks that are separately initialized and trained based on different types or forms of training data, which may be used with cascaded or parallel operation of the plurality of trained neural networks.
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公开(公告)号:US20180174024A1
公开(公告)日:2018-06-21
申请号:US15385504
申请日:2016-12-20
Applicant: Intel Corporation
Inventor: Tsung-Han Lin , Narayan Srinivasa
CPC classification number: G06N3/049 , G06F17/16 , G06N3/0454 , G06N3/063 , G06N3/0635 , G06N3/08
Abstract: A spiking neural network (SNN) is defined that includes artificial neurons interconnected by artificial synapses, the SNN defined to correspond to one or more numerical matrices in an equation such that weight values of the synapses correspond to values in the numerical matrices. An input vector is provided to the SNN to correspond to a numerical vector in the equation. A steady state spiking rate is determined for at least a portion of the neurons in the SNN and an approximate result of a matrix inverse problem corresponding to the equation is determined based on values of the steady state spiking rates.
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公开(公告)号:US20250166115A1
公开(公告)日:2025-05-22
申请号:US18971949
申请日:2024-12-06
Applicant: Intel Corporation
Inventor: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
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