公开(公告)号：US20190052457A1

公开(公告)日：2019-02-14

申请号：US15941114

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Patrick Connor ,  Scott Dubal ,  Andrew J. Herdrich ,  James R. Hearn ,  Kapil Sood

IPC: H04L9/08 ,  G06F3/06 ,  G06F12/06 ,  G06F17/30

Abstract: Technologies for providing efficient sharing of encrypted data in a disaggregated architecture include a sled. The sled includes a set of memory devices and a controller connected to the set of memory devices. The memory controller is to receive, from a first application executed by a compute sled, a data access request to share a data set between the first application and a second application. The data set is encrypted in one or more of the memory devices. Additionally, the controller is to determine, in response to the data access request, a key identifier that uniquely identifies a key that is usable to perform cryptographic operations on the data set. Further, the controller is to send, to an encryption key manager, a request to provide the key corresponding to the key identifier to be used by the second application to decrypt the data set and send, to the second application, a handle associated with an address in the set of memory devices where the data set is located.

公开(公告)号：US20190042388A1

公开(公告)日：2019-02-07

申请号：US16022543

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Ren Wang ,  Bin Li ,  Andrew J. Herdrich ,  Tsung-Yuan C. Tai ,  Ramakrishna Huggahalli

IPC: G06F11/34 ,  G06F12/0811 ,  G06F12/121 ,  G06F13/16 ,  G06F13/42 ,  G06F11/30

Abstract: There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a directly writable cache; and a cache monitoring circuit, including cache counters La to be incremented when a cache line is allocated into the directly writable cache, Lp to be incremented when a cache line is processed by the processor and deallocated from the directly writable cache, and Le to be incremented when a cache line is evicted from the directly writable cache to the memory, wherein the cache monitoring circuit is to determine a direct write policy according to the cache counters.

公开(公告)号：US20180341494A1

公开(公告)日：2018-11-29

申请号：US15607121

申请日：2017-05-26

Applicant: Intel Corporation

Inventor： Kapil Sood ,  Andrew J. Herdrich ,  Scott P. Dubal ,  Patrick L. Connor ,  James Robert Hearn ,  Niall D. McDonnell

IPC: G06F9/38 ,  H04L29/06

Abstract: Generally discussed herein are systems, devices, and methods for network security monitoring (NSM). A hardware queue manager (HQM) may include an input interface to receive first data from at least a first worker thread, queue duplication circuitry to generate a copy of at least a portion of the first data to create first copied data, and an output interface to (a) provide the first copied data to a second worker thread, and/or (b) provide at least a portion of the first data to a third worker thread.

公开(公告)号：US20180329478A1

公开(公告)日：2018-11-15

申请号：US16043738

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Rameshkumar G. Illikkal ,  Ravishankar Iyer ,  Sadagopan Srinivasan ,  Jaideep Moses ,  Srihari Makineni

IPC: G06F1/32 ,  H04W88/02 ,  H04W52/02 ,  G06F12/084 ,  G06F9/4401 ,  G06F9/50 ,  G06F13/24

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

公开(公告)号：US20180212842A1

公开(公告)日：2018-07-26

申请号：US15926866

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Muthuvel M. I ,  Ananth S. Narayan ,  Jaideep Moses ,  Andrew J. Herdrich ,  Rahul Khanna

IPC: H04L12/24

CPC classification number: H04L41/50 ,  H04L41/145 ,  H04L41/5009 ,  H04L41/5025

Abstract: In accordance with some embodiments, a cloud service provider may operate a data center in a way that dynamically reallocates resources across nodes within the data center based on both utilization and service level agreements. In other words, the allocation of resources may be adjusted dynamically based on current conditions. The current conditions in the data center may be a function of the nature of all the current workloads. Instead of simply managing the workloads in a way to increase overall execution efficiency, the data center instead may manage the workload to achieve quality of service requirements for particular workloads according to service level agreements.

公开(公告)号：US20180026904A1

公开(公告)日：2018-01-25

申请号：US15395179

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Johan G. Van De Groenendaal ,  Mrittika Ganguli ,  Ahmad Yasin ,  Andrew J. Herdrich

IPC: H04L12/911 ,  H04L12/851 ,  H04L12/26

Abstract: Technologies for dynamically allocating resources within a self-managed node include a self-managed node to receive quality of service objective data indicative of a performance objective of one or more workloads assigned to the self-managed node. Each workload includes one or more tasks. The self-managed node is also to execute the one or more tasks to perform the one or more workloads, obtain telemetry data as the workloads are performed, determine, as a function of the telemetry data, an adjustment to the allocation of resources among the workloads to satisfy the performance objective, and apply the determined adjustment as the workloads are performed by the self-managed node. Other embodiments are also described and claimed.

公开(公告)号：US20170286114A1

公开(公告)日：2017-10-05

申请号：US15089533

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Yipeng Wang ,  Ren Wang ,  Tsung-Yuan Charles Tai ,  Jr-Shian Tsai

IPC: G06F9/30 ,  G06F12/08 ,  G06F3/06

CPC classification number: G06F9/30043 ,  G06F9/30047 ,  G06F9/3824 ,  G06F9/3836 ,  G06F12/0804 ,  G06F12/0862 ,  G06F2212/6028

Abstract: A processor of an aspect includes a decode unit to decode memory access instructions of a first type and to output corresponding memory access operations, and to decode memory access instructions of a second type and to output corresponding memory access operations. The processor also includes a load store queue coupled with the decode unit. The load store queue includes a load buffer that is to have a plurality of load buffer entries, and a store buffer that is to have a plurality of store buffer entries. The load store queue also includes a buffer entry allocation controller coupled with the load buffer and coupled with the store buffer. The buffer entry allocation controller is to allocate load and store buffer entries based at least in part on whether memory access operations correspond to memory access instructions of the first type or of the second type. Other processors, methods, and systems, are also disclosed.

公开(公告)号：US09727345B2

公开(公告)日：2017-08-08

申请号：US13854001

申请日：2013-03-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Rinat Rappoport ,  Michael Mishaeli ,  Hisham Shafi ,  Oron Lenz ,  Jason W. Brandt ,  Stephen A. Fischer ,  Bret L. Toll ,  Inder M. Sodhi ,  Alon Naveh ,  Ganapati N. Srinivasa ,  Ashish V. Choubal ,  Scott D. Hahn ,  David A. Koufaty ,  Russell J. Fenger ,  Gaurav Khanna ,  Eugene Gorbatov ,  Mishali Naik ,  Andrew J. Herdrich ,  Abirami Prabhakaran ,  Sanjeev S. Sahagirdar ,  Paul Brett ,  Paolo Narvaez ,  Andrew D. Henroid ,  Dheeraj R. Subbareddy

IPC: G06F9/44 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F9/4401 ,  G06F9/45558 ,  G06F9/5077 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/36

Abstract: A heterogeneous processor architecture and a method of booting a heterogeneous processor is described. A processor according to one embodiment comprises: a set of large physical processor cores; a set of small physical processor cores having relatively lower performance processing capabilities and relatively lower power usage relative to the large physical processor cores; and a package unit, to enable a bootstrap processor. The bootstrap processor initializes the homogeneous physical processor cores, while the heterogeneous processor presents the appearance of a homogeneous processor to a system firmware interface.

公开(公告)号：US20170180325A1

公开(公告)日：2017-06-22

申请号：US14979134

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Hari K. Tadepalli ,  Rashmin N. Patel ,  Andrew J. Herdrich ,  Edwin Verplanke

IPC: H04L29/06 ,  H04L12/24

CPC classification number: H04L63/04 ,  G06F21/53 ,  G06F2221/2141 ,  H04L41/0806 ,  H04L41/0893 ,  H04L43/0847 ,  H04L63/102

Abstract: Technologies for enforcing virtual machine network access control include a network computing device that includes a plurality of virtual machines. The network computing device is configured to receive an access request from a virtual function assigned to a requesting virtual machine of the network computing device. The network computing device is additionally configured to determine a first privilege level assigned to the requesting machine and a second privilege level assigned to the destination virtual machine, and determine whether the requesting virtual machine is authorized to access the destination virtual machine based on a comparison of the first and second privilege levels. Upon determining the requesting virtual machine is authorized to access the destination virtual machine, the network computing device is additionally configured to allow the requesting virtual machine access to the destination virtual machine. Other embodiments are described herein.

公开(公告)号：US09448829B2

公开(公告)日：2016-09-20

申请号：US13730491

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Paolo Narvaez ,  Ganapati N. Srinivasa ,  Eugene Gorbatov ,  Dheeraj R. Subbareddy ,  Mishali Naik ,  Alon Naveh ,  Abirami Prabhakaran ,  Eliezer Weissmann ,  Paul Brett ,  Scott D. Hahn ,  Andrew J. Herdrich ,  Gaurav Khanna ,  Russell J. Fenger ,  Bryant E. Bigbee ,  Andrew D. Henroid ,  David A. Koufaty

IPC: G06F9/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/38

CPC classification number: G06F9/45558 ,  G06F9/3885 ,  G06F9/5077 ,  G06F2009/4557

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大的物理处理器核心。