公开(公告)号：US20210027416A1

公开(公告)日：2021-01-28

申请号：US16929790

申请日：2020-07-15

Applicant: Intel Corporation

Inventor： Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jacek Kwiatkowski ,  Ingo Wald ,  Jefferson Amstutz ,  Johannes Guenther ,  Gabor Liktor ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T1/20 ,  G09G5/36 ,  G06F3/147 ,  G06F9/50

Abstract: Systems, apparatuses, and methods may provide for technology to process graphical data, and to modify a runtime environment in a parallel computing platform for a graphic environment.

公开(公告)号：US20200334896A1

公开(公告)日：2020-10-22

申请号：US16865587

申请日：2020-05-04

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer Kp ,  Jonathan Kennedy ,  Abhishek R. Appu ,  Jeffery S. Boles ,  Balaji Vembu ,  Michael Apodaca ,  Slawomir Grajewski ,  Gabor Liktor ,  David M. Cimini ,  Andrew T. Lauritzen ,  Travis T. Schluessler ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Kai Xiao ,  Ankur N. Shah ,  Altug Koker

IPC: G06T15/40 ,  G06T1/20 ,  G06T15/30 ,  G06T15/00 ,  G06T11/40 ,  G06T17/20

Abstract: The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles surface triangles in one or more exclusion zones.

公开(公告)号：US10762686B2

公开(公告)日：2020-09-01

申请号：US16235906

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Scott Janus ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Alexey Supikov ,  Gabor Liktor ,  Carsten Benthin ,  Philip Laws ,  Michael Doyle

IPC: G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US10452552B2

公开(公告)日：2019-10-22

申请号：US15488988

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Andrew T. Lauritzen ,  Gabor Liktor ,  Tomer Bar-On ,  Hugues Labbe ,  John G. Gierach ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker

IPC: G06F12/0862 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0855 ,  G06F9/38 ,  G06T1/20

Abstract: Systems, apparatuses and methods may provide a way to track graphics pipeline operations. More particularly, the systems, apparatuses and methods may provide a way to track operation dependencies between graphics pipeline operations for blocks of pixel samples and stall one or more of the pipeline operations based on the operation dependencies. The systems, apparatuses and methods may further provide cache pre-fetch hardware to monitor processing of blocks of pixel samples and fetch a next block of the pixel samples from the memory into a cache before completion of processing a current block of pixel samples based on one or more of the pipeline operations or a surface state of one or more regions of a screen space.

公开(公告)号：US20180300933A1

公开(公告)日：2018-10-18

申请号：US15489177

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Devan Burke ,  Adam T. Lake ,  Jeffery S. Boles ,  John H. Feit ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Joydeep Ray ,  Subramaniam Maiyuran ,  Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Eric J. Hoekstra ,  Gabor Liktor ,  Jonathan Kennedy ,  Slawomir Grajewski ,  Elmoustapha Ould-Ahmed-Vall

IPC: G06T15/00

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, and a graphics subsystem communicatively coupled to the application processor. The system may include one or more of a draw call re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more draw calls, a workload re-orderer communicatively coupled to the application processor and the graphics subsystem to re-order two or more work items in an order independent mode, a queue primitive included in at least one of the two or more draw calls to define a producer stage and a consumer stage, and an order-independent executor communicatively coupled to the application processor and the graphics subsystem to provide tile-based order independent execution of a compute stage. Other embodiments are disclosed and claimed.

公开(公告)号：US09922396B2

公开(公告)日：2018-03-20

申请号：US15157667

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Gabor Liktor ,  Karthik Vaidyanathan

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/06 ,  G06F12/0871

CPC classification number: G06T1/20 ,  G06F12/0871 ,  G06F2212/1016 ,  G06F2212/302 ,  G06F2212/401 ,  G06T15/06 ,  G06T17/005

Abstract: Incremental encoding of Bounding Volume Hierarchies (BVH) enables coarse quantization of bounding volumes, significantly reducing their memory footprint. However, reducing the size of the BVH alone does not yield a comparable reduction in memory bandwidth in some embodiments. While the bounding volumes of the BVH nodes can be aggressively quantized, the size of the child node pointers remains a significant overhead. A two-level clustering method introduces a memory layout and node addressing scheme, which allows the reordering of BVH nodes to reduce their memory footprint in hardware ray tracing systems using reduced precision ray traversal.

公开(公告)号：US09767602B2

公开(公告)日：2017-09-19

申请号：US14319472

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Gabor Liktor ,  Marco Salvi ,  Karthik Vaidyanathan

IPC: G06T15/80

CPC classification number: G06T15/80 ,  G06T11/40 ,  G06T15/30

Abstract: Various embodiments are generally directed to techniques for reducing processing demands of shading primitives in rendering a 2D screen image from a 3D model. A device includes a clipping component to clip a visible primitive of a 2D screen image derived from of a 3D model within a first area of the screen image covered by a shading pixel to form a polygon representing an intersection of the first area and the visible primitive; a first interpolation component to interpolate at least one attribute of vertices of the visible primitive to each vertex of the polygon; and a second interpolation component to interpolate color values of the vertices of the polygon to a point within a second area covered by a screen pixel of the screen image, the second area smaller than the first area and at least partly coinciding with the first area. Other embodiments are described and claimed.