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公开(公告)号：US12132123B2
公开(公告)日：2024-10-29
申请号：US17398129
申请日：2021-08-10
Inventor： Hiroki Miyake
IPC: H01L29/86 , H01L21/02 , H01L29/861 , H01L31/0352
CPC classification number: H01L29/8611 , H01L21/02414 , H01L21/02483 , H01L21/02565 , H01L31/035236
Abstract: A semiconductor device includes: a p-type region including a super-lattice pseudo mixed crystal region in which a first layer and a second layer are alternately stacked. The first layer includes a gallium oxide based semiconductor. The second layer includes a p type semiconductor made of a material different from the first layer.
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公开(公告)号：US20240296091A1
公开(公告)日：2024-09-05
申请号：US18417093
申请日：2024-01-19
Inventor： TETSURO TAKIZAWA
IPC: G06F11/10 , G06F12/0806
CPC classification number: G06F11/1044 , G06F12/0806 , G06F2212/1032
Abstract: A semiconductor memory device includes a plurality of banks, a sense amplifier, an ECC code generation unit, an error correction unit, a first bus, and a second bus. The banks include a data recording unit in which rewritten data is to be written, and an ECC code recording unit in which an error correction code corresponding to the rewritten data is to be written. The sense amplifier is included in each of the banks and configured to read and write data from and to each of the banks. The ECC code generation unit generates the error correction code. The error correction unit corrects an error of data using the error correction code. The first bus connects the sense amplifier in each of the banks and the error correction unit. The second bus connects the ECC code generation unit and the sense amplifier in each of the banks.
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公开(公告)号：US20240295699A1
公开(公告)日：2024-09-05
申请号：US18415102
申请日：2024-01-17
Inventor： HENG LIU , HIROSHI ANDO , MASATOSHI TSUJI , KOJIRO TACHI
CPC classification number: G02B6/262 , G02B27/0101
Abstract: An optical member includes a light guide body that includes a smooth incident surface, a reflecting and emitting surface disposed to face the smooth incident surface, a reflecting surface continuously arranged with the smooth incident surface, and a smooth emitting surface continuously arranged with the reflecting and emitting surface. The reflecting and emitting surface includes first flat portions configured to emit a part of an incident light, and first reflecting portions configured to reflect another part of the incident light. The reflecting surface includes second flat portions and second reflecting portions configured to reflect the light reflected by the first reflecting portions in different directions toward the smooth emitting surface. The smooth emitting surface is configured to reflect the light reflected by the second flat portions by total reflection and emit the light reflected by the second reflecting portions to the outside.
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74.发明公开公开(公告)号：US20240280667A1
公开(公告)日：2024-08-22
申请号：US18421447
申请日：2024-01-24
Inventor： Masanari TAKAKI
IPC: G01S7/40 , G01S13/58 , G01S13/931
CPC classification number: G01S7/4021 , G01S13/582 , G01S13/931 , G01S13/589
Abstract: A radar signal processing device includes an acquirer, pre-segment generator, and a segment generator. The acquirer acqu.ires ranging point information including position information and speed information at each of ranging points obtained by irradiating radar waves. The pre-segment generator generates a pre-segment by grouping the ranging points as a set of the ranging points based on the acquired ranging point information from the acquirer. The segment generator generates a composite segment by combining the ranging points from a first pre-segment with the ranging points from a second pre-segment as a set of the ranging points based on a positional relationship between the first pre-segment and the second pre-segment. The first pre-segment is one of pre-segments generated by the pre-segment generator. The second pre-segment is another one of the pre-segments generated by the pre-segment generator.
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公开(公告)号：US20240259030A1
公开(公告)日：2024-08-01
申请号：US18391789
申请日：2023-12-21
Inventor： Shotaro WADA , Tomohiro NEZUKA , Yoshikazu FURUTA
Abstract: An analog-to-digital converter includes an input-signal chopping switch, an integrator, an output chopping switch, a quantizer, and a feedback switch. The integrator is located after the input-signal chopping switch. The integrator includes an operational amplifier, an integral capacitor, and an integral-capacitor-chopping input switch being at on an input side of the integral capacitor. The output chopping switch is on an output side of the operational amplifier. The quantizer is located after the output chopping switch. The feedback chopping switch is in a feedback path from an output of the quantizer to an input of the first integrator. The input-signal chopping switch, the integral-capacitor-chopping input switch, the output chopping switch, and the feedback chopping switch execute chopping at an identical frequency. The output chopping switch sets a polarity of an input value of the quantizer to be identical before and after the chopping.
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Patent Agency Ranking
76.发明公开公开(公告)号：US20240250128A1
公开(公告)日：2024-07-25
申请号：US18521014
申请日：2023-11-28
Inventor： HIDEYUKI UEHIGASHI
CPC classification number: H01L29/1608 , H01L29/1045 , H01L29/36 , H01L29/7813
Abstract: A silicon carbide substrate includes a substrate made of silicon carbide and having a Young's modulus of 475 GPa or more at 500° C. measured by a resonance method. A silicon carbide wafer includes: the silicon carbide substrate; and an epitaxial layer formed on the silicon carbide substrate. The epitaxial layer has a thickness within a range of 4 to 40 μm. A silicon carbide semiconductor device includes: the silicon carbide substrate; an epitaxial layer formed on the silicon carbide substrate; and a semiconductor element in which a current flows in a stacking direction of the silicon carbide substrate and the epitaxial layer.
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公开(公告)号：US12047206B2
公开(公告)日：2024-07-23
申请号：US17868057
申请日：2022-07-19
Inventor： Shigeki Otsuka , Hyoungjun Na , Takasuke Ito , Yoshikazu Furuta , Tomohiro Nezuka
IPC: H04L25/02 , H03K17/687
CPC classification number: H04L25/0272 , H03K17/6872 , H04L25/028
Abstract: A differential transmission circuit for a communication device performs bidirectional communication via a differential transmission line. The differential transmission circuit include: output transistors that are turned on and off according to a drive signal during a transmission period; a signal generation unit that generates and outputs the drive signal; short-circuit transistors connected between gates and drains of the output transistors; and a cut off unit that cuts off a supply path of the drive signal between the signal generation unit and the gates of the output transistors. The cut off unit cuts off the supply path of the drive signal during a reception period in which a reception operation is performed by the communication device.
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78.发明公开公开(公告)号：US20240186381A1
公开(公告)日：2024-06-06
申请号：US18494315
申请日：2023-10-25
Inventor： Hideyuki UEHIGASHI , Akiyoshi HORIAI
CPC classification number: H01L29/1608 , H01L21/02378 , H01L21/2011 , H01L29/41766 , H01L29/66068 , H01L29/7813
Abstract: A silicon carbide substrate includes a substrate made of silicon carbide. An emission peak of the substrate at a wavelength of 650 to 750 nm is 4.5 times or more of an emission peak of the substrate at a wavelength of 385 to 408 nm in an electronic excitation. An integral value related to an emission peak of the substrate at a wavelength of 650 to 750 nm is 15 times or more of an integral value related to an emission peak of the substrate at a wavelength of 385 to 408 nm in an electronic excitation.
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公开(公告)号：US20240141550A1
公开(公告)日：2024-05-02
申请号：US18476507
申请日：2023-09-28
Inventor： HIROAKI FUJIBAYASHI , MASATAKE NAGAYA , JUNJI OHARA , SHINICHI HOSHI
CPC classification number: C30B25/10 , C23C16/325 , C23C16/4584 , C23C16/46 , C30B25/12 , C30B29/36
Abstract: A silicon carbide wafer manufacturing apparatus includes a mounting unit disposed in a reaction chamber. The mounting unit includes a susceptor portion having a mounting surface on which a rear surface of a seed substrate is to be mounted, and a guide portion disposed on the susceptor portion in a state of surrounding the seed substrate. The mounting unit is configured such that a first interval between the seed substrate and the guide portion on an upstream side in a step-flow growth direction is narrower than a second interval between the seed substrate and the guide portion on a downstream side in the step-flow growth direction when an epitaxial layer is grown. The guide portion is configured such that a temperature of the guide portion is lower than a temperature of the seed substrate when the epitaxial layer is grown.
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公开(公告)号：US20240126474A1
公开(公告)日：2024-04-18
申请号：US18475359
申请日：2023-09-27
Inventor： Tetsuro TAKIZAWA
IPC: G06F3/06
CPC classification number: G06F3/0656 , G06F3/0613 , G06F3/0673
Abstract: An input output control device between a verification circuit and a semiconductor memory device includes: a first port that receives a read transaction for requesting reading of data in the semiconductor memory device from the verification circuit, and outputs a read response to the verification circuit; a second port that outputs the read transaction to the semiconductor memory device, and receives the read response output from the semiconductor memory device in response to the read transaction; and a buffer device that delays at least one of an output of the read transaction to the semiconductor memory device and an output of the read response to the verification circuit.
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