公开(公告)号：US06867788B1

公开(公告)日：2005-03-15

申请号：US09327512

申请日：1999-06-08

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G06F17/30 ,  G06F19/00 ,  G06Q10/10 ,  G06T11/60

CPC classification number: G06T11/60 ,  G06F17/30554

Abstract: To provide a more flexible and higher level visualization technique for combining a plurality of analysis methods and visual representations, a view composition system, for combining a plurality of visual representations, includes a view manager for managing as a view a set of data for individual visual representation, a view retriever for retrieving from a plurality of views those views that can be combined, and a view composer for combining the views obtained by the view retriever. Optionally, a view displayer, displays the view produced by the view composer. The view composition system can combine a plurality of views using the superimposition of views and neighboring dimensions that have compatible domains.

Abstract translation: 为了提供用于组合多个分析方法和视觉表示的更灵活和更高级别的可视化技术，用于组合多个视觉表示的视图合成系统包括视图管理器，用于管理用于个人视觉的一组数据 表示，用于从多个视图中检索可组合的视图的视图检索器和用于组合由视图检索器获得的视图的视图编辑器。 可选地，视图显示器显示由视图编辑器产生的视图。 视图合成系统可以使用具有兼容域的视图叠加和相邻尺寸来组合多个视图。

公开(公告)号：US06359825B1

公开(公告)日：2002-03-19

申请号：US09428712

申请日：1999-10-28

Applicant: Yoshiharu Aimoto ,  Tohru Kimura ,  Koichi Takeda

Inventor： Yoshiharu Aimoto ,  Tohru Kimura ,  Koichi Takeda

IPC: G11C800

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4096

Abstract: A dynamic memory including a first sense amplifier circuit directly connected to a bit line of a memory cell, a second sense amplifier directly connected to a data input/output circuit, a switching circuit connected between the first sense amplifier circuit and the second sense amplifier circuit. In a reading operation, the switching circuit is controlled to separate the first sense amplifier circuit and the second sense amplifier circuit from each other after data is read out from the memory cell, so that the read-out data is amplified by the second sense amplifier circuit and outputted from the second sense amplifier circuit to an external of the memory. On the other hand, the first sense amplifier circuit amplifies the read-out data and writes back the read-out data to the memory cell. In the writing operation, the switching circuit is controlled to interconnect the first sense amplifier circuit and the second sense amplifier circuit to each other, so that data to be written from an external is written into the memory cell through the first and second sense amplifier circuits.

Abstract translation: 动态存储器包括直接连接到存储单元的位线的第一读出放大器电路，直接连接到数据输入/输出电路的第二读出放大器，连接在第一读出放大器电路和第二读出放大器电路之间的开关电路 。 在读取操作中，在从存储单元读出数据之后，切换电路被控制以将第一读出放大器电路和第二读出放大器电路彼此分开，使得读出数据由第二读出放大器 并从第二读出放大器电路输出到存储器的外部。 另一方面，第一读出放大器电路放大读出的数据并将读出的数据写回存储单元。 在写入操作中，切换电路被控制以将第一读出放大器电路和第二读出放大器电路彼此互连，使得要从外部写入的数据通过第一和第二读出放大器电路被写入存储器单元 。

公开(公告)号：US06311198B1

公开(公告)日：2001-10-30

申请号：US09130503

申请日：1998-08-06

Applicant: Naohiko Uramoto ,  Koichi Takeda

Inventor： Naohiko Uramoto ,  Koichi Takeda

IPC: G06F1500

CPC classification number: G06F17/30707 ,  G06F17/3069 ,  Y10S707/99935

Abstract: In order to efficiently thread n chronologically ordered documents, a similarity among the n documents is calculated and the similarity is employed to create a similarity matrix using time constraints, and is converted into an adjacency matrix for identifying a relationship among the n documents. By applying this threading method that employs the time constraints, a large quantity of article data can be efficiently threaded in the O(n) order. Users can easily access a large quantity of data and can understand the contents.

Abstract translation: 为了有效地对n个时间排序的文档进行线索，计算出n个文档之间的相似度，并且使用相似性来创建使用时间约束的相似矩阵，并且被转换成用于识别n个文档之间的关系的邻接矩阵。 通过应用采用时间约束的这种线程方法，可以以O（n）顺序有效地螺纹化大量的物品数据。 用户可以轻松访问大量数据，并可以了解内容。

公开(公告)号：US5694367A

公开(公告)日：1997-12-02

申请号：US681860

申请日：1996-07-29

Applicant: Hideo Toyoshima ,  Koichi Takeda ,  Shigeru Kuhara

Inventor： Hideo Toyoshima ,  Koichi Takeda ,  Shigeru Kuhara

IPC: G11C11/416 ,  G11C7/06 ,  G11C7/10 ,  G11C11/419 ,  G11C7/02

CPC classification number: G11C7/062 ,  G11C11/419 ,  G11C7/10 ,  G11C7/1048

Abstract: A semiconductor memory includes a plurality of first memory cell arrays, a pair of first common data lines which are provided for the plurality of first memory cell arrays, and a sensing section including a pair of first bipolar transistors whose emitters are respectively connected to the first common data lines and first constant current sources. Each first memory cell arrays includes a plurality of second memory cell arrays, a pair of second common data lines, a first differential amplifier including a second constant current source and a pair of second bipolar transistors whose bases are respectively connected to the second common data lines, whose bases are connected to the second constant current source together, and whose collectors are connected to the first common data lines, and a third constant current source of a second differential amplifier. Each second memory cell arrays includes a plurality of third memory cell arrays, a pair of third common data lines, a pair of third bipolar transistors whose bases are respectively connected to the third common data lines, whose emitters are connected to the third constant current source together to constitute the second differential amplifier, and whose collectors are respectively connected to the second common data lines, and a first control circuit for selectively activating the pair of third bipolar transistors. Each third memory cell arrays includes a pair of bit lines, a plurality of memory cells connected to the pair of bit lines, and a second control circuit for selectively connecting the pair of bit lines to the pair of second common data lines.

Abstract translation: 半导体存储器包括多个第一存储单元阵列，为多个第一存储单元阵列提供的一对第一公共数据线，以及包括一对第一双极晶体管的感测部分，其发射极分别连接到第一存储单元阵列 公共数据线和第一恒流源。 每个第一存储单元阵列包括多个第二存储单元阵列，一对第二公共数据线，包括第二恒流源的第一差分放大器和其基极分别连接到第二公共数据线的一对第二双极晶体管 ，其基极一起连接到第二恒流源，并且其集电极连接到第一公共数据线，以及第二恒定电流源的第二差分放大器。 每个第二存储单元阵列包括多个第三存储单元阵列，一对第三公共数据线，一对第三双极晶体管，其基极分别连接到第三公共数据线，其发射极连接到第三恒流源 一起构成第二差分放大器，并且其集电极分别连接到第二公共数据线，以及第一控制电路，用于选择性地激活该对第三双极晶体管。 每个第三存储单元阵列包括一对位线，连接到该对位线的多个存储单元，以及用于选择性地将一对位线连接到该对第二公共数据线的第二控制电路。

公开(公告)号：US4445182A

公开(公告)日：1984-04-24

申请号：US253854

申请日：1981-06-22

Applicant: Eiichi Morita ,  Yoshihisa Kato ,  Koichi Takeda ,  Takuya Oku

Inventor： Eiichi Morita ,  Yoshihisa Kato ,  Koichi Takeda ,  Takuya Oku

IPC: G05B19/18 ,  G05B19/4093 ,  G05B19/41 ,  G06F15/46

CPC classification number: G05B19/40932 ,  G05B19/182 ,  G05B19/40937 ,  G05B19/40938 ,  G05B19/41 ,  G05B2219/34215 ,  G05B2219/35098 ,  G05B2219/35269 ,  G05B2219/35401 ,  G05B2219/35426 ,  G05B2219/35439 ,  G05B2219/35525 ,  G05B2219/36349 ,  G05B2219/36498 ,  G05B2219/36513 ,  G05B2219/45136 ,  G05B2219/49392 ,  G05B2219/50289 ,  G05B2219/50334 ,  Y02P90/265

Abstract: A method of control of NC machine tools of the type wherein all control data necessary for preparing machining data is inputted into a control device by key switches provided on an operating board. The data necessary for machining a workpiece stored in a microcomputer contained in the NC machine is reduced to the lowest minimum, while various data, such as the paths of movement of tools during rough machining, rough finish machining and finish machining, actually needed for machining the workpiece are successively computed on the basis of the data stored in said microcomputer in advance. Thus, data associated with a variety of workpieces can be processed with a minimum of memory capacity, and complicated shapes having concaves and convexes can accurately be machined in a simple operation.

Abstract translation: PCT No.PCT / JP80 / 00214 Sec。 371日期：1981年6月2日 102（e）日期1981年4月2日PCT提交1980年9月24日PCT公布。 公开号WO81 / 01061 日期：1981年04月16日。一种控制数控机床的方法，其中通过设置在操作板上的键开关将准备加工数据所需的所有控制数据输入控制装置。 将存储在NC机器中的微型计算机中存储的工件加工所需的数据减少到最低的最小值，而粗加工中的刀具运动路径，粗加工精加工和精加工实际上需要加工的各种数据 预先根据存储在所述微计算机中的数据依次计算出工件。 因此，可以以最小的存储容量来处理与各种工件相关联的数据，并且可以在简单的操作中精确地加工具有凹凸的复杂形状。

公开(公告)号：US20120257442A1

公开(公告)日：2012-10-11

申请号：US13463355

申请日：2012-05-03

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: A semiconductor memory device having a read word line, a write word line and a sub-word driver operable to select the read word line using a main word signal and an inverse read block signal. The sub-word line selects the write word line using the main word signal and an inverse write block signal. The sub-word driver has a first inverter circuit using the main word signal as an input and outputting the read word line. The sub-word driver has a first transistor having a drain, a source, and a gate connected to the read word line, a low potential power source, and the inverse write block signal, respectively, and a second transistor having a drain, a source, and a gate connected to a power source terminal of the first inverter circuit, a power source, and the inverse write block signal, respectively, and can select the write word line.

Abstract translation: 具有读字线，写字线和子字驱动器的半导体存储器件，可操作以使用主字信号和反读块信号来选择读字线。 子字线使用主字信号和反写写信号来选择写字线。 子字驱动器具有使用主字信号作为输入并输出读字线的第一反相器电路。 子字驱动器具有分别具有与读取字线连接的漏极，源极和栅极的第一晶体管，低电位电源和反向写入块信号，以及具有漏极的第二晶体管， 源极和连接到第一反相器电路的电源端子的栅极，电源和反向写入块信号，并且可以选择写入字线。

公开(公告)号：US08206197B2

公开(公告)日：2012-06-26

申请号：US12596333

申请日：2008-04-17

Applicant: Hidetaka Nakao ,  Masafumi Inoue ,  Koichi Takeda

Inventor： Hidetaka Nakao ,  Masafumi Inoue ,  Koichi Takeda

IPC: B24B49/00 ,  B24B1/00

CPC classification number: H01L21/67219 ,  B24B37/042 ,  B24B37/345 ,  G05B19/41865 ,  G05B2219/32304 ,  G05B2219/45232 ,  H01L21/02074 ,  H01L21/67276 ,  Y02P90/20

Abstract: A polishing apparatus includes a loading section (14) for placing therein a cassette (12) in which a plurality of polishing objects are housed; a first polishing line (20) and a second polishing line (30) for polishing a polishing object; a cleaning line (40) having cleaning machines (42a, 42b, 42c, 42d) for cleaning the polishing object after polishing and a transport unit (44) for transporting the polishing object; a transport mechanism (50) for transporting the polishing object between the loading section (14), the polishing lines (20, 30) and the cleaning line (40); and a control section for controlling the polishing lines (20, 30), the cleaning line (40) and the transport mechanism (50). The control section determines a polishing start time in each of the first and second polishing lines (20, 30) based on a predicted polishing time in each of the first and second polishing lines (20, 30), a predicted transport time in the transport mechanism (50), a predicted cleaning time in the cleaning line (40) and a predicted cleaning start time to start cleaning by driving the transport unit (44) of the cleaning line (40).

Abstract translation: 抛光装置包括用于放置其中容纳有多个抛光对象的盒（12）的装载部（14）; 用于抛光抛光对象的第一抛光线（20）和第二抛光线（30）; 清洁线（40），其具有用于清洁抛光后的抛光对象物的清洁机（42a，42b，42c，42d）和用于输送抛光对象物的输送单元（44） 用于在加载部分（14），抛光线（20,30）和清洁线（40）之间传送抛光对象的传送机构（50）; 以及用于控制研磨线（20,30），清洁线（40）和输送机构（50）的控制部。 控制部分基于第一和第二研磨线（20,30）中的每一个中的预测的抛光时间来确定第一和第二抛光线（20,30）中的每一个中的抛光开始时间，运送中预测的运送时间 机构（50），清洁管线（40）中的预测清洁时间和通过驱动清洗管线（40）的输送单元（44）开始清洁的预测清洁开始时间。

公开(公告)号：US08199594B2

公开(公告)日：2012-06-12

申请号：US12910536

申请日：2010-10-22

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C7/00

CPC classification number: G11C11/412

Abstract: The SRAM cell is formed by an inverter circuit (P1, N1) using a storage node V2 as an input and a storage node V1 as an output, a load transistor P2 connected between a power source VDD and the storage node V2 using the storage node V1 as an input and the storage node V2 as an output, an access transistor N3 connected between a read bit line RBL and the storage node V1, and an access transistor N4 connected between a write bit line WBL and the storage node V2. When the access transistor N4 is controlled by a write word line WWL, the access transistor N4 can be used as holding control means and writing means for the memory cell, making it possible to obtain a semiconductor device capable of operating at a high speed with a small number of elements.

Abstract translation: SRAM单元由使用存储节点V2作为输入的反相器电路（P1，N1）和作为输出的存储节点V1，使用存储节点连接在电源VDD与存储节点V2之间的负载晶体管P2 V1作为输入，存储节点V2作为输出，连接在读取位线RBL和存储节点V1之间的存取晶体管N3以及连接在写位线WBL与存储节点V2之间的存取晶体管N4。 当访问晶体管N4由写入字线WWL控制时，存取晶体管N4可以用作存储单元的保持控制装置和写入装置，使得可以获得能够以高速操作的半导体器件 少数元素。

公开(公告)号：US08164962B2

公开(公告)日：2012-04-24

申请号：US12585495

申请日：2009-09-16

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C7/00

CPC classification number: G11C7/02 ,  G11C11/417 ,  G11C11/419

Abstract: A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal.

Abstract translation: 半导体存储装置包括SRAM电路，其具有存储数据的第一SRAM单元和放大数据的电位差并存储电位差的第二SRAM单元;输出第一控制信号的字线驱动器电路，用于选择第一 要读/写数据的SRAM单元和用于选择要读/写电位差的第二SRAM单元之一的第二控制信号，放大从位线对输出的读信号的电位差的读出放大器电路 根据第二控制信号选择的第二SRAM单元;以及写入驱动器电路，其将写入信号输出到根据第二控制信号选择的第二SRAM单元的位线对，并且写入信号之间具有电位差， 位线大于读取信号。

公开(公告)号：US08134863B2

公开(公告)日：2012-03-13

申请号：US12923264

申请日：2010-09-13

Applicant: Koichi Takeda

Inventor： Koichi Takeda

IPC: G11C11/00

CPC classification number: G11C5/025

Abstract: A semiconductor device according to the present invention includes a first memory cell array in which a plurality of first memory cells are arranged as a matrix, data being read from or written to the first memory cells, and a second memory cell array in which a plurality of second memory cells amplifying and storing the data of one of the plurality of the first memory cells arranged in a corresponding column are arranged as a matrix. The first memory cell array and the second memory cell array are arranged face to face in the column direction. An area of the second memory cell is larger than that of the first memory cell. An area of the first memory cell array is twice or more as large as that of the second memory cell array.

Abstract translation: 根据本发明的半导体器件包括：第一存储单元阵列，其中多个第一存储单元被布置为矩阵，从第一存储单元读取或写入数据;第二存储单元阵列，其中多个 放置并存储布置在相应列中的多个第一存储单元之一的数据的第二存储单元被布置为矩阵。 第一存储单元阵列和第二存储单元阵列在列方向上面对面布置。 第二存储单元的区域大于第一存储单元的区域。 第一存储单元阵列的面积是第二存储单元阵列的面积的两倍或更多倍。