公开(公告)号：US07669170B2

公开(公告)日：2010-02-23

申请号：US11676185

申请日：2007-02-16

Applicant: John M. Cohn ,  Jason Hibbeler ,  Anthony K. Stamper ,  Jed H. Rankin

Inventor： John M. Cohn ,  Jason Hibbeler ,  Anthony K. Stamper ,  Jed H. Rankin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.

Abstract translation: 提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。 该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。 符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。 布局迁移工具可用于修改现有布局，以实施新的网格要求。

公开(公告)号：US20100041202A1

公开(公告)日：2010-02-18

申请号：US12191633

申请日：2008-08-14

Applicant: Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

Inventor： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

IPC: H01L21/02

CPC classification number: H01L23/5228 ,  H01L21/76816 ,  H01L23/5226 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a second metal line embedded in a second dielectric layer overlies a first metal line embedded in a first dielectric layer. A portion of the second dielectric layer overlying the first metal line is recessed employing a photoresist and the second metal line as an etch mask. A doped semiconductor spacer is formed within the recess to provide a resistive link between the first metal line and the second metal line. In another embodiment, a first metal line and a second metal line are embedded in a dielectric layer. An area of the dielectric layer laterally abutting the first and second metal lines is recessed employing a photoresist and the first and second metal lines as an etch mask. A doped semiconductor spacer is formed on sidewalls of the first and second metal lines, providing a resistive link between the first and second metal lines.

Abstract translation: 在一个实施例中，嵌入在第二介电层中的第二金属线覆盖在嵌入第一介电层中的第一金属线上。 覆盖第一金属线的第二电介质层的一部分使用光致抗蚀剂凹陷，第二金属线作为蚀刻掩模。 在凹槽内形成掺杂半导体衬垫，以在第一金属线和第二金属线之间提供电阻连接。 在另一个实施例中，第一金属线和第二金属线嵌入在电介质层中。 使用光致抗蚀剂和第一和第二金属线作为蚀刻掩模来凹入与第一和第二金属线横向邻接的电介质层的区域。 掺杂半导体衬垫形成在第一和第二金属线的侧壁上，提供第一和第二金属线之间的电阻连接。

公开(公告)号：US20100029021A1

公开(公告)日：2010-02-04

申请号：US12182668

申请日：2008-07-30

Applicant: Brent A. Anderson ,  Robert K. Leidy ,  Jed H. Rankin

Inventor： Brent A. Anderson ,  Robert K. Leidy ,  Jed H. Rankin

IPC: H01L21/66

CPC classification number: G03F7/70866 ,  G03F7/7085 ,  G03F7/70975

Abstract: Methods for real-time contamination, environmental, or physical monitoring of a photomask. An attribute of a photomask is monitored using a sensor of an electronics package attached to the photomask. The methods further include generating one or more sensor signals relating to the monitored attribute with the sensor and transmitting the one or more sensor signals from the electronics package to a control system.

Abstract translation: 光掩模的实时污染，环境或物理监测的方法。 使用附接到光掩模的电子封装的传感器监视光掩模的属性。 所述方法还包括利用所述传感器生成与所监视的属性相关的一个或多个传感器信号，并将所述一个或多个传感器信号从所述电子装置封装传送到控制系统。

公开(公告)号：US07473946B2

公开(公告)日：2009-01-06

申请号：US11276274

申请日：2006-02-22

Applicant: Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211

Abstract: A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation.

Abstract translation: 互补金属氧化物半导体（CMOS）结构包括具有第一台面的半导体衬底，其具有沟道有效水平表面积与沟道有效垂直表面面积的第一比率。 CMOS结构还包括具有大于第一比率的相同表面积的第二比率的第二台面。 具有第一极性的第一器件使用第一台面作为通道，并且受益于增强的垂直结晶取向。 具有与第一极性不同的第二极性的第二装置使用第二台面作为通道，并且受益于增强的水平晶体取向。

公开(公告)号：US07361556B2

公开(公告)日：2008-04-22

申请号：US11495518

申请日：2006-07-31

Applicant: James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

Inventor： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

Abstract: A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

Abstract translation: 通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。 双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

公开(公告)号：US07268397B2

公开(公告)日：2007-09-11

申请号：US11160360

申请日：2005-06-21

Applicant: Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin ,  William F. Clark, Jr.

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin ,  William F. Clark, Jr.

IPC: H01L29/78

CPC classification number: H01L29/78606 ,  H01L27/0248 ,  H01L29/42384 ,  H01L29/785

Abstract: A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.

Abstract translation: 翅片型场效应晶体管具有在衬底上方的绝缘体层和在绝缘体层上方延伸的翅片。 鳍片有一个通道区域，以及源极和漏极区域。 栅极导体位于沟道区域的上方。 绝缘体层包括邻近翅片的散热结构特征，并且栅极导体的一部分接触散热结构特征。 散热结构特征可以包括绝缘体层内的凹槽或延伸穿过绝缘体层的热导体。

公开(公告)号：US07224029B2

公开(公告)日：2007-05-29

申请号：US10707964

申请日：2004-01-28

Applicant: Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

Inventor： Brent A. Anderson ,  Edward J. Nowak ,  Jed H. Rankin

IPC: H01L21/36 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/66803

Abstract: Disclosed is a structure and method for producing a fin-type field effect transistor (FinFET) that has a buried oxide layer over a substrate, at least one first fin structure and at least one second fin structure positioned on the buried oxide layer. First spacers are adjacent the first fin structure and second spacers are adjacent the second fin structure. The first spacers cover a larger portion of the first fin structure when compared to the portion of the second fin structure covered by the second spacers. Those fins that have larger spacers will receive a smaller area of semiconductor doping and those fins that have smaller spacers will receive a larger area of semiconductor doping. Therefore, there is a difference in doping between the first fins and the second fins that is caused by the differently sized spacers. The difference in doping between the first fins and the second fins changes an effective width of the second fins when compared to the first fins.

Abstract translation: 公开了一种用于制造在衬底上具有掩埋氧化层的鳍式场效应晶体管（FinFET）的结构和方法，至少一个第一鳍结构和位于掩埋氧化物层上的至少一个第二鳍结构。 第一间隔件与第一翅片结构相邻，第二间隔件邻近第二翅片结构。 当与由第二间隔物覆盖的第二鳍结构的部分相比时，第一间隔物覆盖第一鳍结构的较大部分。 具有较大间隔物的那些翅片将接收较小的半导体掺杂面积，并且具有较小间隔物的那些翅片将接收更大面积的半导体掺杂。 因此，由不同尺寸的间隔件引起的第一散热片和第二散热片之间的掺杂存在差异。 与第一鳍片相比，第一鳍片和第二鳍片之间的掺杂差异改变了第二鳍片的有效宽度。

公开(公告)号：US07188322B2

公开(公告)日：2007-03-06

申请号：US10906591

申请日：2005-02-25

Applicant: John M. Cohn ,  Jason Hibbeler ,  Anthony K. Stamper ,  Jed H. Rankin

Inventor： John M. Cohn ,  Jason Hibbeler ,  Anthony K. Stamper ,  Jed H. Rankin

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: A circuit layout methology is provided for eliminating the extra processing time and file-space requirements associated with the optical proximity correction (OPC) of a VLSI design. The methodology starts with the design rules for a given manufacturing technology and establishes a new set of layer-specific grid values. A layout obeying these new grid requirements leads to a significant reduction in data preparation time, cost, and file size. A layout-migration tool can be used to modify an existing layout in order to enforce the new grid requirements.

Abstract translation: 提供电路布局方案，用于消除与VLSI设计的光学邻近校正（OPC）相关联的额外处理时间和文件空间要求。 该方法从给定制造技术的设计规则开始，并建立一组新的层特定网格值。 符合这些新网格要求的布局导致数据准备时间，成本和文件大小显着降低。 布局迁移工具可用于修改现有布局，以实施新的网格要求。

公开(公告)号：US07132325B2

公开(公告)日：2006-11-07

申请号：US10731511

申请日：2003-12-09

Applicant: Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

Inventor： Wagdi W. Abadeer ,  Eric Adler ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Jonathan M. McKenna ,  Jed H. Rankin ,  Edward W. Sengle ,  William R. Tonti

IPC: H01L21/8242

CPC classification number: H01L22/34 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for detecting semiconductor process stress-induced defects. The method comprising: providing a polysilicon-bounded test diode, the diode comprising a diffused first region within an upper portion of a second region of a silicon substrate, the second region of an opposite dopant type from the first region, the first region surrounded by a peripheral dielectric isolation, a peripheral polysilicon gate comprising a polysilicon layer over a dielectric layer and the gate overlapping a peripheral portion of the first region; stressing the diode; and monitoring the stressed diode for spikes in gate current during the stress, determining the frequency distribution of the slope of the forward bias voltage versus the first region current at the pre-selected forward bias voltage and monitoring, after stress, the diode for soft breakdown. A DRAM cell may be substituted for the diode. The use of the diode as an antifuse is also disclosed.

公开(公告)号：US07112845B2

公开(公告)日：2006-09-26

申请号：US10064171

申请日：2002-06-18

Applicant: James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

Inventor： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

IPC: H01L27/01

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66818

Abstract: A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.