公开(公告)号：US20060128091A1

公开(公告)日：2006-06-15

申请号：US10905025

申请日：2004-12-10

Applicant: Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

Inventor： Dureseti Chidambarrao ,  Ying Li ,  Rajeev Malik ,  Shreesh Narasimha ,  Haining Yang ,  Huilong Zhu

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L29/66772 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device having dual nitride liners, which provide an increased transverse stress state for at least one FET and methods for the manufacture of such a device. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to the device and applying a second silicon nitride liner adjacent the first silicon nitride liner, wherein at least one of the first and second silicon nitride liners induces a transverse stress in a silicon channel beneath at least one of the first and second silicon nitride liner.

Abstract translation: 本发明提供一种具有双重氮化物衬垫的半导体器件，其为至少一个FET提供增加的横向应力状态以及用于制造这种器件的方法。 本发明的第一方面提供了一种用于制造半导体器件的方法，包括以下步骤：将第一氮化硅衬垫施加到器件上并施加与第一氮化硅衬垫相邻的第二氮化硅衬垫，其中至少一个 第一和第二氮化硅衬垫在第一和第二氮化硅衬里中的至少一个之下的硅沟道中引起横向应力。

公开(公告)号：US20060099729A1

公开(公告)日：2006-05-11

申请号：US10904330

申请日：2004-11-04

Applicant: Haining Yang

Inventor： Haining Yang

IPC: H01L21/00

CPC classification number: H01L21/823468 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823475

Abstract: Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited in/or on the semiconductor substrate. Subsequently a second spacer covering the surface of the first spacer, and a contact liner over at least the gate stack, the second spacer and the silicide, are formed. Then an interlayer dielectric over the contact liner is deposited. Next, a metal contact opening is formed to expose the contact liner over the silicide. Finally, the opening is extended through the contact liner to expose the silicide without exposing the substrate.

Abstract translation: 公开了一种制造场效应晶体管的方法。 在该方法中，形成半导体衬底的顶表面上的栅极叠层，然后在栅极堆叠的侧壁上形成第一间隔物。 接下来，将与第一间隔物自对准的硅化物沉积在半导体衬底中的/或上。 随后，形成覆盖第一间隔物的表面的第二间隔物，以及至少栅极叠层，第二间隔物和硅化物之间的接触衬垫。 然后沉积接触衬垫上的层间电介质。 接下来，形成金属接触开口以使接触衬里暴露在硅化物上。 最后，将开口延伸穿过接触衬垫以暴露硅化物而不暴露衬底。

公开(公告)号：US06924195B2

公开(公告)日：2005-08-02

申请号：US10778795

申请日：2004-02-12

Applicant: Haining Yang

Inventor： Haining Yang

IPC: C23C16/18 ,  C23C16/455 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L28/60 ,  H01L21/28556

Abstract: The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to release metal from the precursor, and subsequently the released metal is deposited over the semiconductor substrate. The invention also includes capacitor constructions, and methods of forming capacitor constructions.

Abstract translation: 本发明包括形成用于半导体结构的含金属物质的方法。 提供半导体衬底，并且在衬底附近提供金属有机前体。 将前体暴露于还原气氛中以从前体释放金属，随后将释放的金属沉积在半导体衬底上。 本发明还包括电容器结构以及形成电容器结构的方法。

公开(公告)号：US20050093078A1

公开(公告)日：2005-05-05

申请号：US10695754

申请日：2003-10-30

Applicant: Victor Chan ,  Haining Yang

Inventor： Victor Chan ,  Haining Yang

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/76 ,  H01L31/062

CPC classification number: H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092

Abstract: Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

公开(公告)号：US20050062133A1

公开(公告)日：2005-03-24

申请号：US10969705

申请日：2004-10-20

Applicant: Ramachandra Divakaruni ,  Jack Mandelman ,  Haining Yang

Inventor： Ramachandra Divakaruni ,  Jack Mandelman ,  Haining Yang

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/60 ,  H01L21/8242 ,  H01L29/00

CPC classification number: H01L21/76897 ,  H01L27/10864 ,  H01L27/10888

Abstract: A short or high leakage path from a metal contact to a P-well can occur when a contact via mask is misaligned with an active area mask, in combination with an overetch into the isolation oxide of an isolation trench which forms a divot in the isolation oxide, exposing the contact junction depletion region or even a P-well on the active area sidewall. This problem is prevented by using an N+ doped polysilicon liner, wherein an outdiffusion of N+ dopant from the poly liner forms an N+ halo extension in the active area silicon, providing a reverse biased junction between the metal contact stud and the P-well. The complementary structure and method of an N-well and P+ dopant are also disclosed

Abstract translation: 当接触通孔掩模与有源区域掩模不对准时，可能会发生从金属接触到P阱的短路或高泄漏路径，以及与隔离沟槽隔离氧化物的隔离结合，隔离沟槽在隔离层中形成阴极 氧化物，暴露接触点耗尽区域或甚至暴露在有源区域侧壁上的P阱。 通过使用N +掺杂多晶硅衬垫来防止这个问题，其中来自多层衬垫的N +掺杂剂的扩散在有源区硅中形成N +卤素延伸，从而在金属接触柱和P阱之间提供反向偏置的结。 还公开了N阱和P +掺杂剂的互补结构和方法

公开(公告)号：US06518610B2

公开(公告)日：2003-02-11

申请号：US09789335

申请日：2001-02-20

Applicant: Haining Yang ,  Dan Gealy ,  Gurtej S. Sandhu ,  Howard Rhodes ,  Mark Visokay

Inventor： Haining Yang ,  Dan Gealy ,  Gurtej S. Sandhu ,  Howard Rhodes ,  Mark Visokay

IPC: H01L27108

CPC classification number: H01L28/75 ,  H01L21/28568 ,  H01L28/55

Abstract: A structure and method are disclosed for forming a capacitor for an integrated circuit. The capacitor includes a rhodium-rich structure, a rhodium oxide layer in direct contact with the rhodium-rich structure, a capacitor dielectric in direct contact with the rhodium oxide layer and a top electrode over the capacitor. The rhodium-rich structure can include rhodium alloys and the capacitor dielectric preferably has a high dielectric constant.

公开(公告)号：US20110188328A1

公开(公告)日：2011-08-04

申请号：US12699933

申请日：2010-02-04

Applicant: Haining Yang ,  Zhongze Wang ,  ChangHo Jung

Inventor： Haining Yang ,  Zhongze Wang ,  ChangHo Jung

IPC: G11C7/00 ,  G11C8/16

CPC classification number: G11C8/16 ,  G11C11/412

Abstract: A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell.

Abstract translation: 多端口RAM电路具有耦合到多个位线和多个位线条的数据输入线。 电路也有多条字线。 存储单元耦合到位线，位线条和字线。 电路还包括控制器，使得字线能够基本上同时从位线写入存储单元。

公开(公告)号：US20110003473A1

公开(公告)日：2011-01-06

申请号：US12881806

申请日：2010-09-14

Applicant: Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

Inventor： Chih-Chao Yang ,  Daniel C. Edelstein ,  Keith Kwong Hon Wong ,  Haining Yang

IPC: H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849

Abstract: An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material.

Abstract translation: 提供了一种互连结构，其中嵌入电介质材料内的导电特征被金属覆盖层封盖，但在最终结构中绝缘材料表面上没有金属残留物。 与现有技术的互连结构相比，本发明的互连结构具有改善的介电击穿强度。 此外，本发明的互连结构对于半导体工业具有更好的可靠性和技术可扩展性。 本发明的互连结构包括具有嵌入其中的至少一个金属封盖的导电特征的电介质材料，其中所述至少一个金属封端的导电特征的顶部在电介质材料的上表面上方延伸。 电介质覆盖层位于电介质材料上，并且封装在电介质材料的上表面上方延伸的所述至少一个金属封盖导电特征的顶部。

公开(公告)号：US07863186B2

公开(公告)日：2011-01-04

申请号：US12334746

申请日：2008-12-15

Applicant: Wai-Kin Li ,  Haining Yang

Inventor： Wai-Kin Li ,  Haining Yang

IPC: H01L21/44

CPC classification number: H01L29/42316 ,  H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  Y10S977/892

Abstract: Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

Abstract translation: 通过用亚光刻，亚临界尺寸，纳米级开口深度“穿孔”硅化物栅极导体，产生完全均匀的硅化栅极导体。 然后沉积硅化物形成金属（例如钴，钨等），覆盖它们并填充穿孔的多晶硅栅极。 退火步骤将多晶硅转化为硅化物。 由于深的穿孔，与硅化物形成金属接触的多晶硅的表面积比常规硅化技术大大增加，导致多晶硅栅极被完全转变成均匀的硅化物组成。 使用自组装二嵌段共聚物来形成用作形成穿孔的蚀刻“模板”的规则的亚光刻纳米尺度图案。

公开(公告)号：US07772119B2

公开(公告)日：2010-08-10

申请号：US12186923

申请日：2008-08-06

Applicant: Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

Inventor： Chih-Chao Yang ,  Haining Yang ,  Keith Kwong Hon Wong

IPC: H01L21/768

CPC classification number: H01L21/76829 ,  H01L21/76834 ,  Y10S438/927

Abstract: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.