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    Feedback control systems with pulse density signal processing capabilities
    72.
    发明授权
    Feedback control systems with pulse density signal processing capabilities 有权

    公开(公告)号：US09966959B2

    公开(公告)日：2018-05-08

    申请号：US15214310

    申请日：2016-07-19

    Applicant: Altera Corporation

    Inventor： Benjamin Peter Jeppesen

    IPC: H03K19/177 ,  H03K19/003 ,  H03K19/21

    CPC classification number: H03K19/17708 ,  H03K19/00346 ,  H03K19/1778 ,  H03K19/21 ,  H04B14/026 ,  H04B14/06

    Abstract: A feedback control system may include a feedback controller for controlling a plant using pulse density signals. The feedback controller may include a pulse density signal generator and a controller logic circuit. The pulse density signal generator may receive input command signals and generate signed or unsigned pulse density input signals. The controller logic may receive the pulse density input signals from the pulse density signal generator and feedback pulse density signals from the plant and may generate corresponding pulse density control signals for controlling the plant based on the input command signals. The controller logic may include a sign change logic, an addition circuit, and an optional amplifier circuit. The pulse density signal generator may also include rate transition circuits for ensuring that the pulse density input signals and the feedback pulse density signals are uncorrelated.

    Zero-offset sampling for clock duty cycle correction
    75.
    发明授权
    Zero-offset sampling for clock duty cycle correction 有权

    公开(公告)号：US09941871B1

    公开(公告)日：2018-04-10

    申请号：US15273920

    申请日：2016-09-23

    Applicant: Altera Corporation

    Inventor： Ker Yon Lau

    IPC: H03K3/017 ,  H03K5/156 ,  H03K19/21

    CPC classification number: H03K5/1565 ,  H03K19/21

    Abstract: Duty cycle sampling circuitry is disclosed that may generate offsets that cancel each other out, thereby improving the accuracy of duty cycle sampling of input clock signals based on sampling clock signals. The input clock input signals may be swapped, or the sampling clock signals may be swapped, or both may be swapped, at various times. Erroneous samples obtained in one configuration can cancel out other erroneous samples obtained in another configuration.

    Magnetically decoupled inductor structures
    76.
    发明授权
    Magnetically decoupled inductor structures 有权

    公开(公告)号：US09941201B1

    公开(公告)日：2018-04-10

    申请号：US15013885

    申请日：2016-02-02

    Applicant: Altera Corporation

    Inventor： Xiaohong Jiang ,  Nathaniel Wright Unger ,  Kyung Suk Oh

    IPC: H01L27/08 ,  H01L21/20 ,  H01L23/522 ,  H01L49/02 ,  H01L23/528

    CPC classification number: H01L23/5227 ,  H01L23/5286 ,  H01L28/10

    Abstract: In one embodiment, an integrated circuit die includes first and second inductor structures, a first ground conductor, a second ground conductor and a conductive trace. The first ground conductor provides a first ground pathway for the first inductor structure. The second ground conductor provides a second ground pathway for the second inductor structure. The conductive trace coupled between the first and second ground conductors may magnetically decouple the first and second inductor structures. In addition, the integrated circuit die may also include conductive guard ring structures that surround the first and second inductor structures. One of the conductive guard ring structures may be connected to the first grounding pathway and the other conductive guard ring structure may be connected to the second grounding pathway. The conductive guard ring structures may further magnetically decouple the first and second inductor structures.

    Communication link control using communication interface and programmable logic circuitry
    79.
    发明授权
    Communication link control using communication interface and programmable logic circuitry 有权

    公开(公告)号：US09929803B1

    公开(公告)日：2018-03-27

    申请号：US15278211

    申请日：2016-09-28

    Applicant: Altera Corporation

    Inventor： Hsinho Wu ,  Mike Peng Li ,  Masashi Shimanouchi

    IPC: H04B10/08 ,  H04B10/079 ,  H04L29/06

    CPC classification number: H04L69/18 ,  H04B10/07955

    Abstract: Systems and methods related to the configuration of data communication links between electrical devices are described. The methods described may consider power efficiency of the data communication link along with bit error rate, latency, data rate, and other specifications. Methods discussed may lead to changes in the data communication link protocol, use of error correction coding scheme, the power consumption and the selection of features employed by the data communication link. Electronic systems capable of implementing the discussed methods may be incorporated in the circuitry of the electrical devices. Methods discussed may change the configuration the data communication link features during the operation of the electrical devices and/or the data communication link.

    REDUCED FLOATING-POINT PRECISION ARITHMETIC CIRCUITRY
    80.
    发明申请
    REDUCED FLOATING-POINT PRECISION ARITHMETIC CIRCUITRY 审中-公开

    公开(公告)号：US20180081632A1

    公开(公告)日：2018-03-22

    申请号：US15272231

    申请日：2016-09-21

    Applicant: Altera Corporation

    Inventor： Martin Langhammer

    IPC: G06F7/487 ,  G06F17/16

    CPC classification number: G06F7/4876 ,  G06F17/16 ,  G06F2207/382 ,  G06F2207/483

    Abstract: The present embodiments relate to performing reduced-precision floating-point arithmetic operations using specialized processing blocks with higher-precision floating-point arithmetic circuitry. A specialized processing block may receive four floating-point numbers that represent two single-precision floating-point numbers, each separated into an LSB portion and an MSB portion, or four half-precision floating-point numbers. A first partial product generator may generate a first partial product of first and second input signals, while a second partial product generator may generate a second partial product of third and fourth input signals. A compressor circuit may generate carry and sum vector signals based on the first and second partial products; and circuitry may anticipate rounding and normalization operations by generating in parallel based on the carry and sum vector signals at least two results when performing the single-precision floating-point operation and at least four results when performing the two half-precision floating-point operations.

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