公开(公告)号：US07881111B2

公开(公告)日：2011-02-01

申请号：US12504307

申请日：2009-07-16

Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

IPC: G11C16/04

CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

Abstract translation: 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

公开(公告)号：US07876613B2

公开(公告)日：2011-01-25

申请号：US12182274

申请日：2008-07-30

Applicant: Sang-Chul Kang ,  Ho-kil Lee ,  Jin-Yub Lee

Inventor： Sang-Chul Kang ,  Ho-kil Lee ,  Jin-Yub Lee

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.

Abstract translation: 提供多位闪存设备。 该多位闪存器件包括存储单元阵列和包括页缓冲器的页缓冲块。 每个页面缓冲器具有单个锁存结构，并且根据加载的数据对存储器单元执行写入操作。 缓冲随机存取存储器（RAM）被配置为在多位程序操作期间存储从外部主机设备提供的程序数据。 提供了控制逻辑，其被配置为控制页面缓冲区块和缓冲器RAM，使得存储在缓冲器RAM中的程序数据被重新加载到页面缓冲器块中，每当在多位程序操作之前编程的数据与当前的数据进行比较 程序。 控制逻辑被配置为在多位程序操作完成之前存储要在缓冲RAM中接下来被编程的数据。

公开(公告)号：US20110013457A1

公开(公告)日：2011-01-20

申请号：US12830903

申请日：2010-07-06

Applicant: Jinman Han

Inventor： Jinman Han

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: Provided are nonvolatile memory devices and programming methods thereof. A non-volatile memory device is programmed by performing a plurality of programming loops on memory cells in a memory cell array and changing a program inhibit voltage applied to bit lines of the memory cells that have completed programming while performing the plurality of programming loops.

Abstract translation: 提供了非易失性存储器件及其编程方法。 通过在存储单元阵列中的存储器单元上执行多个编程循环并改变在执行多个编程循环时施加到已完成编程的存储器单元的位线的程序禁止电压来编程非易失性存储器件。

公开(公告)号：US07869276B2

公开(公告)日：2011-01-11

申请号：US11946893

申请日：2007-11-29

Applicant: Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

Inventor： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC: G11C16/06 ,  G11C16/10 ,  G11C16/22

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring.

Abstract translation: 存储器包括许多存储器区域。 存储区具有多个多级单元。 每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。 第一位线耦合到多级单元的第一列。 第二位线耦合到多电平单元的第二列。 数据缓冲器耦合到第一位线和第二位线，并用于存储要编程到多电平单元中的数据。 保护单元耦合到第一位线，第二位线和数据缓冲器，并且用于防止发生编程错误。

公开(公告)号：US20100329014A1

公开(公告)日：2010-12-30

申请号：US12765230

申请日：2010-04-22

Applicant: Kyu Hee LIM ,  Seung Ho Chang ,  Seong Je Park

Inventor： Kyu Hee LIM ,  Seung Ho Chang ,  Seong Je Park

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C2211/5634 ,  G11C2211/5642

Abstract: A semiconductor memory device includes a memory cell array including an even page cell group and an odd page cell group, and a page buffer configured to read data stored in memory cells of the even page cell group and the odd page cell group and store the read data. The page buffer comprises a first latch configured to store first even page data of the even page cell group when a first read operation is performed, a second latch configured to store odd page data of the odd page cell group when a second read operation is performed, and a third latch configured to store second even page data of the even page cell group when a third read operation is performed.

Abstract translation: 一种半导体存储器件包括一个包括偶数页单元组和奇数页单元组的存储单元阵列，以及一个页缓冲器，被配置为读取存储在偶页单元组和奇数页单元组的存储单元中的数据，并存储读 数据。 页面缓冲器包括第一锁存器，其被配置为当执行第一读取操作时存储偶数页单元组的第一偶数页数据;第二锁存器，被配置为当执行第二读取操作时存储奇数页单元组的奇数页数据 以及第三锁存器，被配置为当执行第三读取操作时存储偶数页单元组的第二偶数页数据。

公开(公告)号：US07813187B2

公开(公告)日：2010-10-12

申请号：US11938603

申请日：2007-11-12

Applicant: Seung-Jae Lee

Inventor： Seung-Jae Lee

IPC: G11C7/00

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C29/00 ,  G11C2211/5621 ,  G11C2211/5642

Abstract: A method for programming a flash memory device including a plurality of memory cells, each storing multi-bit data, includes reading data from selected memory cells. An error of the read data is detected and corrected. Input program data is programmed into the selected memory cells based upon the error-corrected read data.

Abstract translation: 一种用于编程包括存储多位数据的多个存储器单元的闪存器件的方法包括从所选存储单元读取数据。 检测并纠正读取数据的错误。 输入程序数据根据纠错后的读取数据编程到所选存储单元中。

公开(公告)号：US07796439B2

公开(公告)日：2010-09-14

申请号：US12017543

申请日：2008-01-22

Applicant: Fumitaka Arai ,  Takeshi Kamigaichi ,  Atsuhiro Sato

Inventor： Fumitaka Arai ,  Takeshi Kamigaichi ,  Atsuhiro Sato

IPC: G11C11/34 ,  G11C11/06

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5622 ,  G11C2211/5642

Abstract: A semiconductor memory device includes a memory cell array, bit lines, a source line, a sense amplifier, a data buffer, a voltage generating circuit, and a control circuit, the control circuit being configured such that the control circuit writes batchwise the write data, in the plurality of memory cells of the bit lines, the control circuit, after the batchwise write, causes the plurality of first latch circuits to hold the write data once again, and the control circuit executes verify read from the memory cells, and executes, in a case where read data of the plurality of sense amplifier circuits by the verify read disagree with the write data that are held once again in the plurality of first latch circuits, additional write to write batchwise the held write data in the plurality of memory cells once again.

Abstract translation: 半导体存储器件包括存储单元阵列，位线，源极线，读出放大器，数据缓冲器，电压产生电路和控制电路，该控制电路被配置为使得控制电路分批写入写数据 在位线的多个存储单元中，控制电路在分批写入之后使得多个第一锁存电路再次保持写入数据，并且控制电路执行从存储器单元的验证读取，并执行 在通过验证读取的多个读出放大器电路的读取数据与在多个第一锁存电路中再次被保持的写入数据不同时的情况下，对多个存储器中的保持的写入数据进行分批写入 细胞再次。

公开(公告)号：US20100214849A1

公开(公告)日：2010-08-26

申请号：US12647725

申请日：2009-12-28

Applicant: Hyun Jong Jin ,  Jin Haeng Lee

Inventor： Hyun Jong Jin ,  Jin Haeng Lee

IPC: G11C16/06 ,  G11C7/10

CPC classification number: G11C7/1033 ,  G11C7/065 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

Abstract: The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed.

Abstract translation: 当执行程序验证操作时，利用使用第一和第二验证电压的双重验证方法的非易失性存储器件的页面缓冲器包括第一锁存单元，其包括第一锁存器，其被配置为存储输入数据以及程序操作和第一验证操作的结果 使用第一验证电压，以及包括配置为具有比第一锁存器更高的锁存跳变点的第二锁存器的第二锁存单元，并且使用小于第一验证电压的第二验证电压存储第二验证操作的结果 当执行第一验证操作时。

公开(公告)号：US20100097841A1

公开(公告)日：2010-04-22

申请号：US12487165

申请日：2009-06-18

Applicant: Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Andrew John Carter ,  Daniel Reed

Inventor： Yong Lu ,  Harry Hongyue Liu ,  Hai Li ,  Andrew John Carter ,  Daniel Reed

IPC: G11C11/00 ,  G11C7/10

CPC classification number: G11C13/0064 ,  G11C11/1675 ,  G11C11/56 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0088 ,  G11C2211/5622 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2213/79

Abstract: Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.

Abstract translation: 用于将数据传送到存储器的装置和相关方法，例如电阻读出存储器（RSM）。 根据一些实施例，包括逻辑状态序列的输入数据通过在第一写入步骤期间同时向第一多个单位单元中的每个单元写入第一逻辑状态而将第一逻辑状态写入存储器块，并且同时写入 在第二写入步骤期间从序列到第二非重叠多个单位单元中的每一个的第二逻辑状态。

公开(公告)号：US07679980B2

公开(公告)日：2010-03-16

申请号：US11602719

申请日：2006-11-21

Applicant: Thomas Happ ,  Jan Boris Philipp

Inventor： Thomas Happ ,  Jan Boris Philipp

IPC: G11C7/00

CPC classification number: G11C13/0069 ,  G11C11/406 ,  G11C11/40622 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3431 ,  G11C2211/5642 ,  G11C2213/79

Abstract: A memory includes an array of phase change memory cells and a first circuit. The first circuit is for refreshing only memory cells within the array of phase change memory cells that are programmed to non-crystalline states in response to a request for a refresh operation.

Abstract translation: 存储器包括相变存储器单元阵列和第一电路。 第一电路用于仅刷新响应于刷新操作的请求被编程为非结晶状态的相变存储器单元阵列内的存储器单元。