公开(公告)号：US08270223B2

公开(公告)日：2012-09-18

申请号：US12628710

申请日：2009-12-01

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Shuo-Nan Hung ,  Chun-Hsiung Hung

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： A memory device includes a memory sector including a memory sector, a row of select transistors and a number of drivers. The memory sector includes a plurality of word lines each couples to a plurality of memory cells. The row of select transistors select the memory sector and separate the memory sector from an immediately adjacent memory sector in the memory device. Each of the number of drivers is coupled to one of the plurality of word lines. A first one of the drivers is coupled to a first one of the word lines to receive a first control signal to conduct the first word line and a voltage source, and a second one of the drivers is coupled to a second one of the word lines to receive a second control signal to disconnect the second word line from the voltage source.

摘要翻译： 存储器件包括存储器扇区，其包括存储器扇区，一行选择晶体管和多个驱动器。 存储器扇区包括多个字线，每个字线耦合到多个存储器单元。 选择晶体管行选择存储器扇区，并将存储器扇区与存储器件中紧邻的存储器扇区分开。 多个驱动器中的每一个耦合到多个字线中的一个。 驱动器中的第一个被耦合到字线中的第一个以接收第一控制信号以传导第一字线和电压源，并且第二驱动器耦合到第二个字线 以接收第二控制信号以将第二字线与电压源断开。

公开(公告)号：US20120210193A1

公开(公告)日：2012-08-16

申请号：US13456870

申请日：2012-04-26

申请人： Wen-Chiao HO ,  Chin-Hung CHANG ,  Chun-Hsung HUNG ,  Kuen-Long CHANG

发明人： Wen-Chiao HO ,  Chin-Hung CHANG ,  Chun-Hsung HUNG ,  Kuen-Long CHANG

IPC分类号： H03M13/05 ,  G06F11/10 ,  G06F12/00

CPC分类号： H03M13/13 ,  G06F11/1068 ,  H03M13/03 ,  H03M13/3776

摘要： A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.

摘要翻译： 用于检查存储器的读取错误的方法包括以下步骤。 接收到第一个数据片段。 产生根据第一数据片段的第一计数索引，其中第一计数索引对应于第一数据片段中的一种二进制值的数量。 第一个数据片段被写入存储器。 第一数据片段作为第二数据片段从存储器读取。 根据第二数据片段生成第二计数索引。 将第一计数指数与第二计数指数进行比较。

公开(公告)号：US20110085380A1

公开(公告)日：2011-04-14

申请号：US12970222

申请日：2010-12-16

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.

摘要翻译： 一种对存储器进行编程的方法，其中所述存储器包括具有多个多电平单元的许多存储区域。 每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。 耦合到第一和第二位线的保护单元和数据缓冲器防止编程错误发生。 在编程方法的实施例中，对应的数据分别输入到数据缓冲器。 对应于第n阶段的数据被编程到目标多级单元中。 修改对应于第（n + 1）个相位的数据，以使对应于第（n + 1）相的数据与对应于第n相的数据相同，如果目标多电平单元通过编程验证处理 根据第n个编程验证电压。 重复上述步骤直到n等于最大值，n为正整数。

公开(公告)号：US20100082880A1

公开(公告)日：2010-04-01

申请号：US12238719

申请日：2008-09-26

申请人： Chun-Hsiung HUNG ,  Wen-Chiao HO

发明人： Chun-Hsiung HUNG ,  Wen-Chiao HO

IPC分类号： G06F11/14 ,  G06F12/00 ,  G06F12/02

CPC分类号： G11C8/12 ,  G11C29/808

摘要： A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block.

摘要翻译： 预编码装置包括第一存储器电路，地址解码器和替代逻辑电路。 第一存储器电路包括多个存储器块，并且在东部包括替换块。 存储器块由多个相应的物理地址指向。 替换块由替换地址指向。 地址解码器解码输入地址以提供预代码地址。 替代逻辑电路查找地址映射表，其将物理地址中的缺陷物理地址映射到替换地址，以在预代码地址对应于缺陷物理地址时将前缀地址映射到替换地址。 替代逻辑电路相应地将代码前数据预编码到替换块。

公开(公告)号：US20100054045A1

公开(公告)日：2010-03-04

申请号：US12204009

申请日：2008-09-04

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C7/00

CPC分类号： G11C16/24 ,  G11C16/26

摘要： A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line.

摘要翻译： 存储器包括多个存储区域，每个存储器区域包括目标存储器单元，源极线，位线和读取控制电路。 源极线耦合到目标存储器单元的第一端子。 位线耦合到目标存储器单元的第二端子。 读取控制电路用于选择性地向源极线施加工作电压。

公开(公告)号：US20090201060A1

公开(公告)日：2009-08-13

申请号：US12027285

申请日：2008-02-07

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： H03L7/00

CPC分类号： H03K5/135 ,  H03K5/06 ,  H03K2005/00195

摘要： A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.

摘要翻译： 提供了应用在SMD块中的时钟同步电路。 时钟同步电路包括多个时钟同步单元级。 时钟同步电路可以通过使用时钟同步单元的每一级中的前向延迟单元，反射镜控制单元或后向延迟单元的新颖的电路设计来实现时钟同步的目的，或者通过使用短脉冲发生电路来产生 用于触发前级延迟单元各级的输出时钟的短脉冲。

公开(公告)号：US20080304337A1

公开(公告)日：2008-12-11

申请号：US12174115

申请日：2008-07-16

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

IPC分类号： G11C7/00

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C11/5671

摘要： A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2n bits, n is a positive integer. The method for accessing memory includes the following steps: Firstly, threshold voltages of the storage are defined into 2n level respectively, wherein each of the 2n level corresponds to a storage status of n bits, and most significant bits of the storage statuses which level 0 to level 2n/2−1 correspond to are different from most significant bits of the storage statuses which level 2n/2 to level 2n−1 correspond to. Next, a target data is divided into n portions and the divided target data is written into n temporary memories respectively. Then, n bits of the target data are written into the multi-level cell. Each of the n bits data is collected from each of the n temporary memories.

摘要翻译： 提供了访问存储器的方法。 存储器包括许多多级单元，每个单元具有至少一个能存储2n位的存储器，n是正整数。 访问存储器的方法包括以下步骤：首先，将存储器的阈值电压分别定义为2n级，其中2n级中的每一级对应于n位的存储状态，存储状态的最高有效位为0级 等级2n / 2-1对应于不同于2n / 2到2n-1级对应的存储状态的最高有效位。 接下来，目标数据被分成n个部分，分割的目标数据被分别写入n个临时存储器。 然后，将目标数据的n位写入多级单元。 从n个临时存储器中的每一个收集n位数据中的每一个。

公开(公告)号：US08259521B2

公开(公告)日：2012-09-04

申请号：US12190715

申请日：2008-08-13

申请人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Wen-Chiao Ho ,  Kuen-Long Chang

IPC分类号： G11C29/00

CPC分类号： G11C29/10 ,  G11C29/12005

摘要： A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells.

摘要翻译： 提供了一种用于测试多芯片封装的方法和电路。 多芯片封装至少包括存储器芯片，并且存储器芯片包括多个存储器单元。 该方法包括对存储器单元执行正常读取操作，以检查从存储器单元读取的数据是否与存储器单元中的预置数据相同; 以及对所述存储器单元执行特殊读取操作，以检查从所述存储器单元读取的数据是否与期望值相同，其中所述期望值与存储在所述存储器单元中的数据无关。

公开(公告)号：US08223559B2

公开(公告)日：2012-07-17

申请号：US12970222

申请日：2010-12-16

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/12 ,  G11C16/10 ,  G11C16/34 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.

摘要翻译： 一种对存储器进行编程的方法，其中所述存储器包括具有多个多电平单元的许多存储区域。 每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。 耦合到第一和第二位线的保护单元和数据缓冲器防止编程错误发生。 在编程方法的实施例中，对应的数据分别输入到数据缓冲器。 对应于第n阶段的数据被编程到目标多级单元中。 修改对应于第（n + 1）个相位的数据，以使对应于第（n + 1）相的数据与对应于第n相的数据相同，如果目标多电平单元通过编程验证处理 根据第n个编程验证电压。 重复上述步骤直到n等于最大值，n为正整数。

公开(公告)号：US20110173512A1

公开(公告)日：2011-07-14

申请号：US13070008

申请日：2011-03-23

申请人： Wen-Chiao HO ,  Ching-Hung Chang ,  Chung-Hsiung Hung ,  Kuen-Long Chang

发明人： Wen-Chiao HO ,  Ching-Hung Chang ,  Chung-Hsiung Hung ,  Kuen-Long Chang

IPC分类号： H03M13/05 ,  G06F11/07 ,  H03M13/29 ,  G06F11/10

CPC分类号： H03M13/13 ,  G06F11/1068 ,  H03M13/03 ,  H03M13/3776

摘要： A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index.

摘要翻译： 用于检查存储器的读取错误的方法包括以下步骤。 接收到第一个数据片段。 产生根据第一数据片段的第一计数索引，其中第一计数索引对应于第一数据片段中的一种二进制值的数量。 第一个数据片段被写入存储器。 第一数据片段作为第二数据片段从存储器读取。 根据第二数据片段生成第二计数索引。 将第一计数指数与第二计数指数进行比较。