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    Selective Deposition of Barrier Layer
    61.
    发明申请
    Selective Deposition of Barrier Layer 有权

    公开(公告)号：US20210313223A1

    公开(公告)日：2021-10-07

    申请号：US16837968

    申请日：2020-04-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

    Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

    Structure and Method for Interconnection with Self-Alignment
    62.
    发明申请
    Structure and Method for Interconnection with Self-Alignment 有权

    公开(公告)号：US20210265208A1

    公开(公告)日：2021-08-26

    申请号：US17314877

    申请日：2021-05-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-I Yang ,  Yu-Chieh Liao ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3105

    Abstract: The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

    Metal capping layer and methods thereof
    64.
    发明授权
    Metal capping layer and methods thereof 有权

    公开(公告)号：US11075113B2

    公开(公告)日：2021-07-27

    申请号：US16270057

    申请日：2019-02-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shao-Kuan Lee ,  Cheng-Chin Lee ,  Hsin-Yen Huang ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L21/76 ,  H01L21/28 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321

    Abstract: A method and structure for forming an enhanced metal capping layer includes forming a portion of a multi-level metal interconnect network over a substrate. In some embodiments, the portion of the multi-level metal interconnect network includes a plurality of metal regions. In some cases, a dielectric region is disposed between each of the plurality of metal regions. By way of example, a metal capping layer may be deposited over each of the plurality of metal regions. Thereafter, in some embodiments, a self-assembled monolayer (SAM) may be deposited, where the SAM forms selectively on the metal capping layer, while the dielectric region is substantially free of the SAM. In various examples, after selectively forming the SAM on the metal capping layer, a thermal process may be performed, where the SAM prevents diffusion of the metal capping layer during the thermal process.

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