公开(公告)号：US12300487B2

公开(公告)日：2025-05-13

申请号：US16559062

申请日：2019-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen-Yu Liu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/02 ,  G03F7/004 ,  G03F7/16

Abstract: A method of forming a photoresist pattern includes forming an upper layer including a floating additive polymer over a photoresist layer formed on a substrate. The photoresist layer is selectively exposed to actinic radiation. The photoresist layer is developed to form a pattern in the photoresist layer, and the upper layer is removed. The floating additive polymer is a siloxane polymer.

公开(公告)号：US12222654B2

公开(公告)日：2025-02-11

申请号：US17378507

申请日：2021-07-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ming-Hui Weng ,  Chen-Yu Liu ,  Cheng-Han Wu ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/32 ,  G03F1/82 ,  G03F7/00 ,  G03F7/30 ,  G03F7/40

Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

公开(公告)号：US20240387240A1

公开(公告)日：2024-11-21

申请号：US18785410

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US12106961B2

公开(公告)日：2024-10-01

申请号：US17581671

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： An-Ren Zi ,  Yahru Cheng ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  G03F7/32 ,  H01L21/308

CPC classification number: H01L21/0274 ,  H01L21/3081

Abstract: A method for forming a semiconductor device is provided. The method includes applying a photoresist composition over a substrate, thereby forming a photoresist layer over the substrate; performing a first baking process to the photoresist layer; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; performing a second baking process to the photoresist layer; and developing the photoresist layer having the pattern therein using a developer, thereby forming a patterned photoresist layer. The first baking process and the second baking process are conducted under an ambient atmosphere having a humidity level ranging from 55% to 100%.

公开(公告)号：US12085855B2

公开(公告)日：2024-09-10

申请号：US17220705

申请日：2021-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Siao-Shan Wang ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/039 ,  G03F7/004 ,  G03F7/027 ,  G03F7/038 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/40 ,  C08L25/08 ,  C08L33/10

CPC classification number: G03F7/027 ,  G03F7/0045 ,  G03F7/0392 ,  G03F7/168 ,  G03F7/2004 ,  C08L25/08 ,  C08L33/10

Abstract: A method for manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a patterned photoresist. The photoresist composition includes a photoactive compound and a resin comprising a radical-active functional group and an acid labile group.

公开(公告)号：US11971659B2

公开(公告)日：2024-04-30

申请号：US16584234

申请日：2019-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chih Ho ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/004 ,  G03F7/012 ,  G03F7/038 ,  G03F7/16

CPC classification number: G03F7/0387 ,  G03F7/0125 ,  G03F7/0382 ,  G03F7/0388 ,  G03F7/168

Abstract: A photoresist composition includes a conjugated resist additive, a photoactive compound, and a polymer resin. The conjugated resist additive is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline. The polyacetylene, polythiophene, polyphenylenevinylene, polyfluorene, polypryrrole, the polyphenylene, and polyaniline includes a substituent selected from the group consisting of an alkyl group, an ether group, an ester group, an alkene group, an aromatic group, an anthracene group, an alcohol group, an amine group, a carboxylic acid group, and an amide group. Another photoresist composition includes a polymer resin having a conjugated moiety and a photoactive compound. The conjugated moiety is one or more selected from the group consisting of a polyacetylene, a polythiophene, a polyphenylenevinylene, a polyfluorene, a polypryrrole, a polyphenylene, and a polyaniline.

公开(公告)号：US11703765B2

公开(公告)日：2023-07-18

申请号：US17150317

申请日：2021-01-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yang Lin ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: G03F7/30 ,  G03F7/36 ,  G03F7/038 ,  G03F7/039 ,  G03F7/38 ,  G03F7/40 ,  G03F7/20 ,  G03F7/32 ,  G03F7/004 ,  B82Y40/00 ,  B82Y30/00

CPC classification number: G03F7/30 ,  G03F7/0045 ,  G03F7/0382 ,  G03F7/0392 ,  G03F7/0397 ,  G03F7/2004 ,  G03F7/32 ,  G03F7/36 ,  G03F7/38 ,  G03F7/40 ,  B82Y30/00 ,  B82Y40/00

Abstract: A photoresist composition includes a photoactive compound and a polymer. The polymer has a polymer backbone including one or more groups selected from:




The polymer backbone includes at least one group selected from B, C-1, or C-2, wherein ALG is an acid labile group, and X is linking group.

公开(公告)号：US11626285B2

公开(公告)日：2023-04-11

申请号：US16991996

申请日：2020-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： An-Ren Zi ,  Ching-Yu Chang ,  Chin-Hsiang Lin

IPC: H01L21/027 ,  H01L21/67

Abstract: A method of manufacturing a semiconductor device includes forming a first protective layer over an edge portion of a first main surface of a semiconductor substrate. A metal-containing photoresist layer is formed over the first main surface of the semiconductor substrate. The first protective layer is removed, and the metal-containing photoresist layer is selectively exposed to actinic radiation. A second protective layer is formed over the edge portion of the first main surface of the semiconductor substrate. The selectively exposed photoresist layer is developed to form a patterned photoresist layer, and the second protective layer is removed.

公开(公告)号：US11164956B2

公开(公告)日：2021-11-02

申请号：US16548918

申请日：2019-08-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chin-Hsiang Lin ,  Teng-Chun Tsai ,  Akira Mineji ,  Huang-Lin Chao

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/49 ,  H01L21/311 ,  H01L21/321 ,  H01L29/78

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

公开(公告)号：US20210294203A1

公开(公告)日：2021-09-23

申请号：US17340991

申请日：2021-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Chien-Cheng Chen ,  Hsin-Chang Lee ,  Chia-Jen Chen ,  Pei-Cheng Hsu ,  Yih-Chen Su ,  Gaston Lee ,  Tran-Hui Shen

IPC: G03F1/24 ,  G03F7/20 ,  G03F1/54 ,  G03F1/38

Abstract: A lithography mask includes a substrate, a reflective structure disposed over a first side of the substrate, and a patterned absorber layer disposed over the reflective structure. The lithography mask includes a first region and a second region that surrounds the first region in a top view. The patterned absorber layer is located in the first region. A substantially non-reflective material is located in the second region. The lithography mask is formed by forming a reflective structure over a substrate, forming an absorber layer over the reflective structure, defining a first region of the lithography mask, and defining a second region of the lithography mask. The defining of the first region includes patterning the absorber layer. The second region is defined to surround the first region in a top view. The defining of the second region includes forming a substantially non-reflective material in the second region.