公开(公告)号：US20220375798A1

公开(公告)日：2022-11-24

申请号：US17882165

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49

Abstract: A method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. The first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.

公开(公告)号：US20220359680A1

公开(公告)日：2022-11-10

申请号：US17814325

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/417 ,  H01L29/40 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L27/092 ,  H01L29/66

Abstract: Methods for forming contacts to source/drain regions and gate electrodes in low- and high-voltage devices and devices formed by the same are disclosed. In an embodiment a device includes a first channel region in a substrate adjacent a first source/drain region; a first gate over the first channel region; a second channel region in the substrate adjacent a second source/drain region, a top surface of the second channel region being below a top surface of the first channel region; a second gate over the second channel region; an ILD over the first gate and the second gate; a first contact extending through the ILD and coupled to the first source/drain region; and a second contact extending through the ILD, coupled to the second source/drain region, and having a width greater a width of the first contact and a height greater than a height of the first contact.

公开(公告)号：US20220359654A1

公开(公告)日：2022-11-10

申请号：US17813980

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Ji-Cheng Chen ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/49

Abstract: A semiconductor device including a barrier layer surrounding a work function metal layer and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region over the semiconductor substrate; a second channel region over the first channel region; gate dielectric layers surrounding the first channel region and the second channel region; work function metal layers surrounding the gate dielectric layers; and barrier layers surrounding the work function metal layers, a first barrier layer surrounding the first channel region being merged with a second barrier layer surrounding the second channel region.

公开(公告)号：US20220352336A1

公开(公告)日：2022-11-03

申请号：US17869430

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/06

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

公开(公告)号：US20220336636A1

公开(公告)日：2022-10-20

申请号：US17230224

申请日：2021-04-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yoh-Rong Liu ,  Wen-Kai Lin ,  Che-Hao Chang ,  Chi On Chui ,  Yung-Cheng Lu ,  Li-Chi Yu ,  Sen-Hong Syue

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

公开(公告)号：US20220336619A1

公开(公告)日：2022-10-20

申请号：US17854749

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hung-Chin Chung ,  Chung-Chiang Wu ,  Hsuan-Yu Tung ,  Kuan-Chang Chiu ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/8234

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.

公开(公告)号：US20220336591A1

公开(公告)日：2022-10-20

申请号：US17854244

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/40 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. The gate electrode includes a first work function metal; a second work function metal over the first work function metal; and a first metal residue at an interface between the first work function metal and the second work function metal, wherein the first metal residue has a metal element that is different than a metal element of the first work function metal.

公开(公告)号：US11450686B2

公开(公告)日：2022-09-20

申请号：US17106516

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Bo-Feng Young ,  Yu-Ming Lin ,  Chi On Chui

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/78 ,  H01L21/28 ,  H01L27/1159 ,  H01L27/11585 ,  H01L29/786

Abstract: A device includes a first channel; a second channel above the first channel; and a gate structure surrounding the first and second channels, wherein the gate structure includes a ferroelectric (FE) layer surrounding the first and second channels and a gate metal layer surrounding the FE layer. The device further includes two first electrodes connected to two sides of the first channel; two second electrodes connected to two sides of the second channel; a dielectric layer between the first and the second electrodes; and an inner spacer layer between the two first electrodes and the gate structure.

公开(公告)号：US20220278000A1

公开(公告)日：2022-09-01

申请号：US17663321

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Ping Wang ,  Ting-Gang Chen ,  Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/764

Abstract: A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

公开(公告)号：US11430698B2

公开(公告)日：2022-08-30

申请号：US16877708

申请日：2020-05-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Han Tsai ,  Chung-Chiang Wu ,  Cheng-Lung Hung ,  Weng Chang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/28 ,  H01L27/088 ,  H01L29/49

Abstract: A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.