Systems and methods for symbol-spaced pattern-adaptable dual loop clock recovery for high speed serial links

    公开(公告)号:US11902408B2

    公开(公告)日:2024-02-13

    申请号:US18078631

    申请日:2022-12-09

    CPC classification number: H04L7/0016 H03L7/0807

    Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

    Fast external pixel compensation in a display panel

    公开(公告)号:US11615739B1

    公开(公告)日:2023-03-28

    申请号:US17678366

    申请日:2022-02-23

    Abstract: A method of compensating for change in pixel and a display device incorporating such method are presented. The method includes dividing pixels into groups including a previous group L−1, a current group L and a next group L+1; determining Aconverged[L] and Bconverged[L] for each pixel in the current group L; for each pixel in the current group L, determining a first moving average Amean[L] and a second moving average Bmean[L] as follows: A mean [ L ] = A ⁢ mean [ L - 1 ] ⁢ ( K - 1 ) + A [ L ] K , B mean [ L ] = B ⁢ mean [ L - 1 ] ⁢ ( K - 1 ) + B [ L ] K , wherein Amean[L−1] is a first moving average of a pixel in the corresponding column in the previous group L−1, Bmean[L−1] is a second moving average of a pixel in the corresponding column in the previous group L−1, and K is a moving average window; and for the next group L+1, setting a first initial value A0[L+1] and a second initial value A0[L+1] of each pixel to Amean[L] and Bmean[L].

    Systems and methods for symbol-spaced pattern-adaptable dual loop clock recovery for high speed serial links

    公开(公告)号:US11546127B2

    公开(公告)日:2023-01-03

    申请号:US17508898

    申请日:2021-10-22

    Abstract: A clock recovery circuit may include: a data slicer configured to output data values based on an input signal, a first error block, a phase adjustment loop including: a first error slicer configured to generate a first error signal based on a comparison of a threshold voltage and an input voltage, wherein the first error block is configured to selectively output the first error signal in response to a first pattern in the output data values, a second error block configured to selectively output the first error signal in response to a second pattern in the output data values, and a voltage threshold modification circuitry configured to adjust the threshold voltage based on output of the second error block, a voltage-controlled oscillator, wherein the data slicer and the first error slicer are clocked based on output of the voltage-controlled oscillator.

    Replica pixel for stand-alone test of display driver

    公开(公告)号:US11341879B2

    公开(公告)日:2022-05-24

    申请号:US17185237

    申请日:2021-02-25

    Abstract: A replica pixel for testing a display IC that includes a driving circuit that drives a display panel and a sensing circuit that senses a received current is presented. The replica pixel includes a replica pixel transistor, which has a first terminal switchably coupled to a power source, a gate coupled to a first node of a capacitor, and a second terminal coupled to a second node of the capacitor. The first node of the capacitor is switchably coupled to a reference voltage Vref. The second node of the capacitor is switchably coupled to a coupling node, wherein the coupling node selectively couples to either the driving circuit or the sensing circuit. The replica pixel is approximately a real pixel without the display element, and may be used to test the display IC without assembling the display IC with a display panel.

    REPLICA PIXEL FOR STAND-ALONE TEST OF DISPLAY DRIVER

    公开(公告)号:US20220130298A1

    公开(公告)日:2022-04-28

    申请号:US17185237

    申请日:2021-02-25

    Abstract: A replica pixel for testing a display IC that includes a driving circuit that drives a display panel and a sensing circuit that senses a received current is presented. The replica pixel includes a replica pixel transistor, which has a first terminal switchably coupled to a power source, a gate coupled to a first node of a capacitor, and a second terminal coupled to a second node of the capacitor. The first node of the capacitor is switchably coupled to a reference voltage Vref. The second node of the capacitor is switchably coupled to a coupling node, wherein the coupling node selectively couples to either the driving circuit or the sensing circuit. The replica pixel is approximately a real pixel without the display element, and may be used to test the display IC without assembling the display IC with a display panel.

    Fully differential front end for sensing

    公开(公告)号:US11087656B2

    公开(公告)日:2021-08-10

    申请号:US16656447

    申请日:2019-10-17

    Abstract: A system and method for sensing drive current in a pixel. In some embodiments, the system includes: a first pixel, a second pixel, a differential sensing circuit, a reference current source, and a control circuit. The differential sensing circuit may have a first input, a second input, and an output, the first input being connected to a node at which a reference current generated by the reference current source is subtracted from a first pixel current, the first pixel current including a current generated by the first pixel. The second input may be configured to receive a second pixel current, the second pixel current including a current generated by the second pixel. The output may be configured to produce an output signal based on a difference between a current received at the first input and a current received at the second input.

    Content adaptive display interface
    69.
    发明授权

    公开(公告)号:US10796660B2

    公开(公告)日:2020-10-06

    申请号:US16243968

    申请日:2019-01-09

    Abstract: Provided is a method of reducing power consumption by a display device including an encoder for receiving a stream of data, and for compressing the data, a TX rate-buffer for receiving and storing the compressed data, a PHY for receiving the compressed data, a RX rate-buffer for receiving and storing the compressed data, and a decoder for receiving the compressed data, and for decompressing the compressed data to reconstruct original data, the method including placing the PHY a SLEEP state to reduce power consumption of the PHY when the TX rate-buffer transmits a last bit of the compressed data in the TX rate-buffer to the PHY, and placing the PHY in a TRANSMIT/ACTIVE state when a fullness of the TX rate-buffer reaches a reference threshold, or a last bit of compressed data corresponding to a last pixel of a line of pixels is placed in the TX rate-buffer.

    Method and apparatus for duty-cycle correction in a serial data transmitter

    公开(公告)号:US10699669B2

    公开(公告)日:2020-06-30

    申请号:US16057037

    申请日:2018-08-07

    Abstract: A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

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