公开(公告)号：US5805603A

公开(公告)日：1998-09-08

申请号：US779068

申请日：1997-01-07

Applicant: Takashi Araki ,  Yasuhiro Konishi ,  Hisashi Iwamoto

Inventor： Takashi Araki ,  Yasuhiro Konishi ,  Hisashi Iwamoto

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C7/1072

Abstract: A synchronous semiconductor memory device is provided with a delay circuit between an input latch circuit and a pad. The synchronous semiconductor memory device can operate at a higher speed since respective external input signals supplied to a plurality of pads are delayed such that the time required for transmission from respective pads to the input latch circuit is equal, and that skew is eliminated.

Abstract translation: 同步半导体存储器件在输入锁存电路和焊盘之间设置延迟电路。 由于提供给多个焊盘的各个外部输入信号被延迟使得从各个焊盘传输到输入锁存电路所需的时间相等，同步半导体存储器件可以更高的速度工作，并且消除了偏斜。

公开(公告)号：US5764590A

公开(公告)日：1998-06-09

申请号：US735149

申请日：1996-10-22

Applicant: Hisashi Iwamoto ,  Yasuhiro Konishi

Inventor： Hisashi Iwamoto ,  Yasuhiro Konishi

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/408 ,  G11C8/00

CPC classification number: G11C7/1039 ,  G11C7/1006

Abstract: A synchronous DRAM includes a selector which supplies 2 bits of serial data signals from one data input/output terminal to two input/output line pairs as parallel data signals in x8 configuration mode, and supplies 2 bits of parallel data signals from both data input/output terminals directly to two input/output line pairs in x16 configuration mode. Therefore, the synchronous DRAM allows switching of bit configuration, and it takes 2-bits prefetch configuration in x8 configuration mode, and signal pipeline configuration in x16 configuration mode.

Abstract translation: 同步DRAM包括一个选择器，它将一个数据输入/输出端子的2位串行数据信号作为并行数据信号以x8配置模式提供给两个输入/输出线对，并从两个数据输入/输出端口提供2位并行数据信号， 输出端子直接连接到x16配置模式下的两个输入/输出线对。 因此，同步DRAM允许位配置的切换，并且在x8配置模式下需要2位预取配置，并在x16配置模式下进行信号流水线配置。

公开(公告)号：US5629897A

公开(公告)日：1997-05-13

申请号：US524927

申请日：1995-09-08

Applicant: Hisashi Iwamoto ,  Yasuhiro Konishi

Inventor： Hisashi Iwamoto ,  Yasuhiro Konishi

IPC: G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C8/00

CPC classification number: G11C7/222 ,  G11C11/406 ,  G11C7/1072 ,  G11C7/22

Abstract: A refresh control circuit of a DLL circuit responds to an auto refresh detection signal AR and a self refresh detection signal SR to inhibit input of clock signals ECLK and RCLK to a phase comparator and to a voltage control delay circuit. The DLL circuit can be stopped in a mode where an internal clock signal is not required to reduce power consumption.

Abstract translation: DLL电路的刷新控制电路响应自动刷新检测信号AR和自刷新检测信号SR，以禁止对相位比较器和电压控制延迟电路的时钟信号ECLK和RCLK的输入。 可以以不需要内部时钟信号来降低功耗的模式停止DLL电路。

公开(公告)号：US5629895A

公开(公告)日：1997-05-13

申请号：US639997

申请日：1996-04-30

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC: G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5583813A

公开(公告)日：1996-12-10

申请号：US461916

申请日：1995-06-05

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC: G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5544121A

公开(公告)日：1996-08-06

申请号：US463565

申请日：1995-06-05

Applicant: Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

Inventor： Katsumi Dosaka ,  Masaki Kumanoya ,  Kouji Hayano ,  Akira Yamazaki ,  Hisashi Iwamoto ,  Hideaki Abe ,  Yasuhiro Konishi ,  Katsumitsu Himukashi ,  Yasuhiro Ishizuka ,  Tsukasa Saiki

IPC: G06F12/08 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00 ,  G11C8/12 ,  G11C11/00 ,  G11C13/00

CPC classification number: G11C8/00 ,  G11C11/005 ,  G11C11/4076 ,  G11C11/4097 ,  G11C11/413 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1045 ,  G11C7/22 ,  G11C8/12 ,  G06F12/0893 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/2245 ,  Y02B60/1225

Abstract: A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

公开(公告)号：US5530379A

公开(公告)日：1996-06-25

申请号：US427186

申请日：1995-04-21

Applicant: Yasuhiro Konishi ,  Takashi Araki ,  Hisashi Iwamoto

Inventor： Yasuhiro Konishi ,  Takashi Araki ,  Hisashi Iwamoto

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/094

CPC classification number: G11C7/1051 ,  H03K19/018585

Abstract: First and second transistors are connected via a first switch. Second and third transistors are connected in parallel via a second switch. Either an input signal or an output ground voltage is applied to the gate of a third transistor via a third switch. In a LVTTL version, the first switch is on and the second switch is off. By the third switch, the output ground voltage is applied to the gate of the third transistor. As a result, first and second, transistors are arranged in series between the output power supply voltage and the output ground voltage, resulting in an output buffer circuit corresponding to a LVTTL. In a GTL version, the first switch is off and the second switch is on. An input signal is applied to the gate of the third transistor by the third switch. As a result, second and third transistors are arranged in parallel to form an open drain. This can be used as an output buffer circuit corresponding to a GTL.

Abstract translation: 第一和第二晶体管经由第一开关连接。 第二和第三晶体管经由第二开关并联连接。 输入信号或输出接地电压通过第三开关施加到第三晶体管的栅极。 在LVTTL版本中，第一个开关打开，第二个开关关闭。 通过第三开关，输出接地电压被施加到第三晶体管的栅极。 结果，第一和第二晶体管串联布置在输出电源电压和输出接地电压之间，产生对应于LVTTL的输出缓冲电路。 在GTL版本中，第一个开关关闭，第二个开关打开。 输入信号通过第三开关施加到第三晶体管的栅极。 结果，第二和第三晶体管平行布置以形成开漏。 这可以用作对应于GTL的输出缓冲电路。

公开(公告)号：US5517462A

公开(公告)日：1996-05-14

申请号：US381586

申请日：1995-01-31

Applicant: Hisashi Iwamoto ,  Yasumitsu Murai ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

Inventor： Hisashi Iwamoto ,  Yasumitsu Murai ,  Yasuhiro Konishi ,  Naoya Watanabe ,  Seiji Sawada

IPC: G11C11/407 ,  F02B75/02 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C13/00

CPC classification number: G11C7/222 ,  G11C7/1072 ,  F02B2075/027

Abstract: In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in word line shunt regions (WS). The connection switches (BS) are arranged in the crossing between the local I/O line pairs and global I/O line pairs. Each small memory array in the activated memory array is connected to the corresponding global I/O line pair through the local I/O line pair. Thereby, a plurality of bits can be simultaneously read without increasing an area occupied by interconnections. The control of connection switch is made using a sense amplifier activation signal. Global I/O lines are precharged/equalized after data are transferred to read data registers provided for data output terminal for sequential data output or into selected memory cells. External clock signal is frequency-divided to produce phase-shifted internal clock signals which are used for producing internal voltage through charge operation.

公开(公告)号：US5473178A

公开(公告)日：1995-12-05

申请号：US223187

申请日：1994-04-05

Applicant: Yasuhiro Konishi

Inventor： Yasuhiro Konishi

IPC: G11C11/402 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10808

Abstract: A DRAM includes an N-type well formed on a main surface of a P-type semiconductor substrate, an N-type impurity region formed on the main surface of the P-type semiconductor substrate, a P-type impurity region formed in the N-type well to be a storage node of a memory capacitor, and a polycrystalline silicon layer for connecting the P-type impurity region and the N-type impurity region. The N-type impurity layer, the P-type impurity layer, and the polycrystalline silicon layer constitute the storage node of the memory capacitor, and electrons of minority carriers flowing from the substrate to the N-type impurity layer are recombined with holes flowing from the N-type well to the P-type impurity layer.

Abstract translation: DRAM包括在P型半导体衬底的主表面上形成的N型阱，形成在P型半导体衬底的主表面上的N型杂质区，形成在N型杂质区中的N型杂质区 型是存储电容器的存储节点，以及用于连接P型杂质区域和N型杂质区域的多晶硅层。 N型杂质层，P型杂质层和多晶硅层构成存储电容器的存储节点，并且从衬底流到N型杂质层的少数载流子的电子与从 N型阱到P型杂质层。

公开(公告)号：US5469099A

公开(公告)日：1995-11-21

申请号：US45387

申请日：1993-04-13

Applicant: Yasuhiro Konishi

Inventor： Yasuhiro Konishi

IPC: G06F1/24 ,  H03K17/22 ,  H03K5/13

CPC classification number: G06F1/24 ,  H03K17/223

Abstract: A first signal generation circuit generates a signal which rises from the ground level to a second level when a prescribed time elapses after an external supply potential starts to rise from the ground level to a first level. A second signal generation circuit outputs a power-on reset signal which falls when the signal outputted from the first signal generation circuit exceeds a first prescribed level and an internal supply potential for an internal circuit outputted from internal supply potential generation means exceeds a second prescribed level.

Abstract translation: 第一信号发生电路在外部电源电位从地电平开始上升到第一电平之后经过规定时间时，产生从地电平上升到第二电平的信号。 第二信号发生电路输出当从第一信号发生电路输出的信号超过第一规定电平时下降的上电复位信号，并且从内部供电电位产生装置输出的内部电路的内部电源电压超过第二规定电平 。