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公开(公告)号：US20150160963A1
公开(公告)日：2015-06-11
申请号：US14306816
申请日：2014-06-17
CPC分类号： G06F9/45558 , G06F9/45533 , G06F9/4856 , G06F9/5077 , G06F12/1009 , G06F2009/4557 , G06F2009/45583 , G06F2009/45595 , H04L67/1008
摘要： A process can be scheduled between first and second hosts that using a virtual file system that is shared between the hosts can be used. The process, running on a first hypervisor of the first host, can be scheduled to run on a second hypervisor of the second host. A file can be created that includes the data content of the process address space for the file. The file can be mapped address space of the virtual file system. Data from the physical memory of the first host can be transferred to physical memory of the second host using page fault routines.
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公开(公告)号：US12038841B2
公开(公告)日：2024-07-16
申请号：US17713264
申请日：2022-04-05
发明人： Tu-An T. Nguyen , Matthias Klein , Gregory William Alexander , Jason D. Kohl , Winston Herring , Timothy Bronson , Christian Jacobi
IPC分类号： G06F12/08 , G06F9/34 , G06F9/38 , G06F12/0815 , G06F12/084 , G06F12/0897
CPC分类号： G06F12/084 , G06F9/34 , G06F9/3816 , G06F12/0815 , G06F12/0897
摘要： Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.
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公开(公告)号：US11579874B2
公开(公告)日：2023-02-14
申请号：US17354302
申请日：2021-06-22
发明人： Christoph Raisch , Marco Kraemer , Frank Siegfried Lehnert , Matthias Klein , Jonathan D. Bradbury , Christian Jacobi , Peter Dana Driever , Brenton Belmar
IPC分类号： G06F9/30 , G06F13/16 , G06F9/4401
摘要： An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.
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公开(公告)号：US11334503B2
公开(公告)日：2022-05-17
申请号：US16775716
申请日：2020-01-29
发明人： Christoph Raisch , Marco Kraemer , Frank Siegfried Lehnert , Matthias Klein , Jonathan D. Bradbury , Christian Jacobi , Brenton Belmar , Peter Dana Driever
摘要： An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.
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公开(公告)号：US11226839B2
公开(公告)日：2022-01-18
申请号：US16286990
申请日：2019-02-27
发明人： Matthias Klein , Bruce Conrad Giamei , Anthony Thomas Sofia , Mark S. Farrell , Scott Swaney , Timothy Siegel
摘要： A system is provided and includes a plurality of machines. The plurality of machines includes a first generation machine and a second generation machine. Each of the plurality of machines includes a machine version. The first generation machine executes a first virtual machine and a virtual architecture level. The second generation machine executes a second virtual machine and the virtual architecture level. The virtual architecture level provides a compatibility level for a complex interruptible instruction to the first and second virtual machines. The compatibility level is architected for a lowest common denominator machine version across the plurality of machines. The compatibility level includes a lowest common denominator indicator identifying the lowest common denominator machine version.
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公开(公告)号：US11188503B2
公开(公告)日：2021-11-30
申请号：US16793113
申请日：2020-02-18
IPC分类号： G06F16/00 , G06F16/174 , G06F16/22 , G06F11/30 , G06F16/21
摘要： Compression of data is facilitated by locating matches within the data to be compressed. A first technique is used to determine whether there is at least one matching string in the data to be compressed, and a second technique, different from the first technique, is used to determine whether there is at least one matching record in the data to be compressed. Based on there being at least one matching string in the data to be compressed, at least one indication of the at least one matching string is provided to an encoder to facilitate compression of the data. Further, based on there being at least one matching record in the data to be compressed, at least one indication of the at least one matching record is provided to the encoder to facilitate compression of the data. It is transparent to the encoder whether the first technique or the second technique is used to provide one or more matches.
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公开(公告)号：US20210216430A1
公开(公告)日：2021-07-15
申请号：US16738311
申请日：2020-01-09
摘要： Aspects of the invention include efficient generation of instrumentation data for direct memory access operations. A non-limiting example apparatus includes an instrumentation component, residing in a cache in communication with a plurality of processing units, an accelerator, and a plurality of input output interfaces. The cache includes a direct memory access monitor that receives events from the accelerator its respective I/O interface and stores DMA state and latency for each event. The cache also includes a bucket including a DMA counter and a latency counter in communication with the DMA monitor, wherein the bucket stores in the DMA counter a count of DMAs coming from a source and stores in the latency counter the latency measured for each DMA coming from the source.
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68.发明授权公开(公告)号：US11042462B2
公开(公告)日：2021-06-22
申请号：US16559999
申请日：2019-09-04
摘要： Identifying computer program execution characteristics for determine relevance of pattern instruction executions to determine characteristics of a computer program. Filters are utilized to determine which subsequent occurrences of execution of at least one computer instruction are relevant to a counter based on execution characteristics of the at least one computer instruction where the counter counts the subsequent occurrences of execution of at least one computer instruction following prior executions of the same at least one computer instruction.
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公开(公告)号：US11005496B2
公开(公告)日：2021-05-11
申请号：US16668061
申请日：2019-10-30
IPC分类号： H03M7/34 , H03M7/30 , G06F9/38 , G06F15/173
摘要： A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.
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公开(公告)号：US10985778B2
公开(公告)日：2021-04-20
申请号：US16741974
申请日：2020-01-14
发明人： Timothy Siegel , Mark Farrell , Bruce Giamei , Matthias Klein , Ashutosh Misra , Simon Weishaupt , Girish Gopala Kurup
IPC分类号： H03M7/34 , H03M13/01 , G06F9/50 , H03M13/00 , H03M7/40 , G06F7/58 , G06F9/30 , G06F9/38 , H03M7/30
摘要： Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
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