公开(公告)号：US20200013138A1

公开(公告)日：2020-01-09

申请号：US16512036

申请日：2019-07-15

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  David M. Cimini ,  Elmoustapha Ould-Ahmed-Vall ,  Jacek Kwiatkowski ,  Philip R. Laws ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/50 ,  G06T15/00 ,  G06T15/50

Abstract: Systems, apparatuses and methods may provide a way to monitor, by a process monitor, one or more processing factors of one or more client devices hosting one or more user sessions. More particularly, the systems, apparatuses and methods may provide a way to generate, responsively, a scene generation plan based on one or more of a digital representation of an N dimensional space or at least one of the one or more processing factors, and generate, by a global scene generator, a global scene common to the one or more client devices based on the digital representation of the space. The systems, apparatuses and methods may further provide for performing, by a local scene generator, at least a portion of the global illumination based on one or more of the scene generation plan, or application parameters.

公开(公告)号：US20190304055A1

公开(公告)日：2019-10-03

申请号：US16446946

申请日：2019-06-20

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Altug Koker ,  Joydeep Ray

IPC: G06T1/20 ,  G06T15/00

Abstract: One embodiment provides for a general-purpose graphics processing unit multiple processing elements having a single instruction, multiple thread (SIMT) architecture, the multiple processing elements to perform hardware multithreading during execution of multiple warps of threads, wherein a warp is a group of parallel threads; a scheduler to schedule a set of sub-warps to the multiple processing elements at sub-warp granularity, wherein a sub-warp is a sub-group of parallel threads, a warp includes multiple sub-warps, and the scheduler is to schedule threads in a first sub-warp of a first warp of threads to execute concurrently with the threads in a second sub-warp of a second warp of threads; and a logic unit including hardware or firmware logic, the logic unit to group active threads for execution on the multiple processing elements.

公开(公告)号：US20190295211A1

公开(公告)日：2019-09-26

申请号：US16377315

申请日：2019-04-08

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  Dukhwan Kim

IPC: G06T1/20 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06F9/46

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

公开(公告)号：US10410311B2

公开(公告)日：2019-09-10

申请号：US15062691

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Kritika Bala ,  Murali Ramadoss ,  Hema Nalluri ,  Jeffery Boles ,  Jeffrey Frizzell ,  Joseph Koston

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/48

Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.

公开(公告)号：US20190197657A1

公开(公告)日：2019-06-27

申请号：US16293044

申请日：2019-03-05

Applicant: Intel Corporation

Inventor： Altug Koker ,  Ingo Wald ,  David Puffer ,  Subramaniam M. Maiyuran ,  Prasoonkumar Surti ,  Balaji Vembu ,  Guei-Yuan Lueh ,  Murali Ramadoss ,  Abhishek R. Appu ,  Joydeep Ray

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/30 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06T1/20 ,  G06F9/3009 ,  G06F9/30185 ,  G06F9/3851 ,  G06F9/461 ,  G06F9/4843

Abstract: One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute blocks, each compute block including multiple processing clusters configured for parallel operation, wherein each of the multiple compute blocks is independently preemptable. In one embodiment a preemption hint can be generated for source code during compilation to enable a compute unit to determine an efficient point for preemption.

公开(公告)号：US10332302B2

公开(公告)日：2019-06-25

申请号：US15489090

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Murali Ramadoss ,  David I. Standring ,  Shruti A. Sethi ,  Jeffrey S. Frizzell ,  Alan M. Curtis ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06F12/02 ,  G06T15/00

Abstract: In an example, an apparatus comprises a plurality of execution units, and logic, at least partially including hardware logic, to create a scatter gather list in memory and collect a plurality of operating statistics for the plurality of execution units using the scatter gather list. Other embodiments are also disclosed and claimed.

公开(公告)号：US10310861B2

公开(公告)日：2019-06-04

申请号：US15477017

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G06T1/20 ,  G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  G06F9/46 ,  G06T1/60 ,  G06F9/52 ,  G06F9/54 ,  G06F15/16 ,  G06F12/08 ,  G06F15/76

Abstract: An apparatus to facilitate thread scheduling is disclosed. The apparatus includes logic to store barrier usage data based on a magnitude of barrier messages in an application kernel and a scheduler to schedule execution of threads across a plurality of multiprocessors based on the barrier usage data.

公开(公告)号：US20190130635A1

公开(公告)日：2019-05-02

申请号：US16233610

申请日：2018-12-27

Applicant: Intel Corporation

Inventor： Murali Ramadoss ,  Balaji Vembu ,  Hema C. Nalluri ,  Michael Apodaca ,  Jeffery S. Boles

IPC: G06T15/80 ,  G06F9/48 ,  G06T1/20

Abstract: By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.

公开(公告)号：US10241921B2

公开(公告)日：2019-03-26

申请号：US15488961

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Prasoonkumar Surti ,  Kamal Sinha ,  Kiran C. Veernapu ,  Balaji Vembu

IPC: G06F12/08 ,  G06F12/0888 ,  G06F13/42 ,  G06F13/40 ,  G06T1/20

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive, in a read/modify/write (RMW) pipeline, a cache access request from a requestor, wherein the cache request comprises a cache set identifier associated with requested data in the cache set, determine whether the cache set associated with the cache set identifier is in an inaccessible invalid state, and in response to a determination that the cache set is in an inaccessible state or an invalid state, to terminate the cache access request. Other embodiments are also disclosed and claimed.

公开(公告)号：US20190034576A1

公开(公告)日：2019-01-31

申请号：US15845788

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Balaji Vembu ,  Santosh Tripathy ,  Altug Koker ,  Pattabhiraman K

IPC: G06F17/50 ,  G06F1/32

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for router-based transaction routing for toggle reduction. An integrated circuit includes a transmitter circuit, receiver circuits, and a multicast bus coupled between the transmitter circuit and the receiver circuits. The multicast bus includes a first flow router circuit to route a multicast signal to a first receiver circuit of the plurality of receiver circuits and not route the multicast signal to a second receiver circuit of the plurality of receiver circuits.