公开(公告)号：US20240095201A1

公开(公告)日：2024-03-21

申请号：US18459311

申请日：2023-08-31

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  Bryan White ,  Balaji Vembu ,  Hema Chand Nalluri ,  Kritika Bala

IPC: G06F13/24 ,  G06F13/16

CPC classification number: G06F13/24 ,  G06F13/1668 ,  G06T1/20

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

公开(公告)号：US12197358B2

公开(公告)日：2025-01-14

申请号：US18459311

申请日：2023-08-31

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  Bryan White ,  Balaji Vembu ,  Hema Chand Nalluri ,  Kritika Bala

IPC: G06F9/48 ,  G06F13/16 ,  G06F13/24 ,  G06T1/20

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

公开(公告)号：US20170256019A1

公开(公告)日：2017-09-07

申请号：US15062691

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Kritika Bala ,  Murali Ramadoss ,  Hema Nalluri ,  Jeffery Boles ,  Jeffrey Frizzell ,  Joseph Koston

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F9/4881 ,  G06F2009/45579

Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.

公开(公告)号：US20230298125A1

公开(公告)日：2023-09-21

申请号：US17827444

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Jeffery S. Boles ,  David Cowperthwaite ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Aravindh Anantaraman ,  Michael Apodaca ,  Kenneth Daxer

IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T1/60 ,  G06F9/4881 ,  G06F9/5061 ,  G06F9/505 ,  G06T2200/16

Abstract: Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

公开(公告)号：US20230297526A1

公开(公告)日：2023-09-21

申请号：US17832305

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  Bryan White ,  Balaji Vembu ,  Hema Chand Nalluri ,  Kritika Bala

IPC: G06F13/24 ,  G06F13/16

CPC classification number: G06F13/24 ,  G06F13/1668 ,  G06T1/20

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

公开(公告)号：US20230297440A1

公开(公告)日：2023-09-21

申请号：US17827373

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Jeffery S. Boles ,  Hema Chand Nalluri ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala

IPC: G06F9/50 ,  G06T1/20

CPC classification number: G06F9/5077 ,  G06F9/5016 ,  G06T1/20

Abstract: Described herein is a partitionable graphics processor having a plurality of flexibly partitioned processing resources. One embodiment provides a graphics processor comprising a plurality of processing resources configurable to be flexibly partitioned into a plurality of resource partitions and circuitry to compose multiple graphics processor device partitions from the plurality of resource partitions. The multiple graphics processor device partitions are configurable to be asymmetrically composed of different types of functional units.

公开(公告)号：US20230297421A1

公开(公告)日：2023-09-21

申请号：US17827346

申请日：2022-05-27

Applicant: Intel Corporation

Inventor： David Cowperthwaite ,  Kenneth Daxer ,  Aditya Navale ,  Prasoonkumar Surti ,  Arthur Hunter ,  Hema Chand Nalluri ,  Jeffery S. Boles ,  Vasanth Ranganathan ,  Joydeep Ray ,  David Puffer ,  Aravindh Anantaraman ,  Ankur Shah ,  Vidhya Krishnan ,  Kritika Bala ,  Michael Apodaca

IPC: G06F9/48 ,  G06T1/60 ,  G06T1/20 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06T1/60 ,  G06T1/20 ,  G06F9/5038 ,  G06F9/5055

Abstract: Described herein is a partitional graphics processor having multiple hard partitions with separate software execution and fault domains. One embodiment provides a graphics processor comprising a system interface and a plurality of graphics processing resources coupled with the system interface. The plurality of graphics processing resources is configurable to be partitioned into a plurality of isolated device partitions, each isolated device partition configured for fault isolation and independent concurrent execution of workloads associated with a plurality of clients, and the system interface is configured to present each of the plurality of isolated device partitions as a virtual function.

公开(公告)号：US11748283B1

公开(公告)日：2023-09-05

申请号：US17832305

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： David Puffer ,  Ankur Shah ,  Niranjan Cooray ,  Bryan White ,  Balaji Vembu ,  Hema Chand Nalluri ,  Kritika Bala

IPC: G06F9/48 ,  G06F12/084 ,  G06F13/24 ,  G06F13/16 ,  G06T1/20

CPC classification number: G06F13/24 ,  G06F13/1668 ,  G06T1/20

Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.

公开(公告)号：US10410311B2

公开(公告)日：2019-09-10

申请号：US15062691

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Kritika Bala ,  Murali Ramadoss ,  Hema Nalluri ,  Jeffery Boles ,  Jeffrey Frizzell ,  Joseph Koston

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/48

Abstract: Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a submission queue of multiple work items for execution on the one or more graphics engines of the graphics processing subsystem. The graphics scheduler can be configured to build the submission queue via a write to a memory mapped address that is mapped to logic within the graphics processing subsystem and to explicitly submit the submission queue to the graphics engine after the build of the submission queue.