公开(公告)号：US20230195503A1

公开(公告)日：2023-06-22

申请号：US17553359

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Michael Cole ,  Pattabhiraman K ,  Ankita A. Agarwal

IPC: G06F9/46

CPC classification number: G06F9/466

Abstract: Methods, systems and apparatuses may provide for technology that includes configuration registers to maintain state information, a filter coupled to the configuration registers, the filter to extract transactions of interest from a plurality of incoming transactions based on the state information, wherein the transactions of interest are extracted on a transaction-by-transaction basis, a first hardware path coupled to the filter, the first hardware path to generate a count of the transactions of interest on a cycle-by-cycle basis, a second hardware path coupled to the filter, the second hardware path to measure a total latency of the transactions of interest on the cycle-by-cycle basis, and an output interface coupled to the first hardware path and the second hardware path, the output interface to determine an average latency of the transactions of interest based on the count of the transactions of interest and the total latency of the transactions of interest.

公开(公告)号：US11475623B2

公开(公告)日：2022-10-18

申请号：US17141431

申请日：2021-01-05

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Pattabhiraman K ,  Balaji Vembu ,  Altug Koker ,  Niranjan L. Cooray ,  Josh B. Mastronarde

IPC: G06T15/00 ,  G06F9/455 ,  G06T1/60 ,  G09G5/36 ,  G09G5/00 ,  G09G5/393 ,  G06F9/48 ,  G06F9/50 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

公开(公告)号：US20220261347A1

公开(公告)日：2022-08-18

申请号：US17732308

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter,, JR. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/0802 ,  G06F9/30

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US20220180467A1

公开(公告)日：2022-06-09

申请号：US17428534

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Aravindh Anantaraman ,  Valentin Andrei ,  Abhishek Appu ,  Sean Coleman ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Pattabhiraman K ,  SungYe Kim ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Elmoustapha Ould-Ahmed-Vall ,  Vasanth Ranganathan ,  James Valerio

IPC: G06T1/20 ,  G06F12/0804 ,  G06F12/0811 ,  G06T1/60

Abstract: Systems and methods for updating remote memory side caches in a multi-GPU configuration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a first memory, a first memory side cache memory, a first communication fabric, and a first memory management unit (MMU). The graphics processor includes a second graphics processing unit (GPU) having a second memory, a second memory side cache memory, a second memory management unit (MMU), and a second communication fabric that is communicatively coupled to the first communication fabric. The first MMU is configured to control memory requests for the first memory, to update content in the first memory, to update content in the first memory side cache memory, and to determine whether to update the content in the second memory side cache memory.

公开(公告)号：US20220179787A1

公开(公告)日：2022-06-09

申请号：US17428530

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/0802 ,  G06F9/30

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US11354770B2

公开(公告)日：2022-06-07

申请号：US17182256

申请日：2021-02-23

Applicant: INTEL CORPORATION

Inventor： Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  Balaji Vembu ,  Pattabhiraman K ,  Matthew B. Callaway

IPC: G06F13/14 ,  G06T1/60 ,  G06T15/00 ,  G06F9/455 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

公开(公告)号：US11341212B2

公开(公告)日：2022-05-24

申请号：US16792822

申请日：2020-02-17

Applicant: INTEL CORPORATION

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Pattabhiraman K ,  Balaji Vembu ,  Altug Koker

IPC: G06F21/10 ,  G06F12/14 ,  G06F12/0895 ,  G06F9/455 ,  G06F12/0815 ,  G06T15/00 ,  H04N19/00 ,  H04N21/4405

Abstract: An apparatus and method for protecting content in a graphics processor. For example, one embodiment of an apparatus comprises: encode/decode circuitry to decode protected audio and/or video content to generate decoded audio and/or video content; a graphics cache of a graphics processing unit (GPU) to store the decoded audio and/or video content; first protection circuitry to set a protection attribute for each cache line containing the decoded audio and/or video data in the graphics cache; a cache coherency controller to generate a coherent read request to the graphics cache; second protection circuitry to read the protection attribute to determine whether the cache line identified in the read request is protected, wherein if it is protected, the second protection circuitry to refrain from including at least some of the data from the cache line in a response.

公开(公告)号：US20220156202A1

公开(公告)日：2022-05-19

申请号：US17590362

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Elmoustapha Ould-Ahmed-Vall ,  Abhishek Appu ,  Aravindh Anantaraman ,  Valentin Andrei ,  Durgaprasad Bilagi ,  Varghese George ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Pattabhiraman K ,  SungYe Kim ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Xinmin Tian

IPC: G06F12/123 ,  G06F12/0891 ,  G06T1/60 ,  G06F12/0875

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

公开(公告)号：US20190034576A1

公开(公告)日：2019-01-31

申请号：US15845788

申请日：2017-12-18

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Balaji Vembu ,  Santosh Tripathy ,  Altug Koker ,  Pattabhiraman K

IPC: G06F17/50 ,  G06F1/32

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for router-based transaction routing for toggle reduction. An integrated circuit includes a transmitter circuit, receiver circuits, and a multicast bus coupled between the transmitter circuit and the receiver circuits. The multicast bus includes a first flow router circuit to route a multicast signal to a first receiver circuit of the plurality of receiver circuits and not route the multicast signal to a second receiver circuit of the plurality of receiver circuits.

公开(公告)号：US10152632B2

公开(公告)日：2018-12-11

申请号：US15483841

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Radhakrishnan Venkataraman ,  James M. Holland ,  Sayan Lahiri ,  Pattabhiraman K ,  Kamal Sinha ,  Chandrasekaran Sakthivel ,  Daniel Pohl ,  Vivek Tiwari ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle ,  Devan Burke

IPC: G06K9/00 ,  G09G5/10 ,  G09G5/391

Abstract: Systems, apparatuses, and methods may provide for technology to dynamically control a display in response to ocular characteristic measurements of at least one eye of a user.