公开(公告)号：US10599582B2

公开(公告)日：2020-03-24

申请号：US15276025

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Vidhya Krishnan ,  Niranjan L. Cooray ,  Murali Ramadoss

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/1009 ,  G06F12/0802 ,  G06F12/1045 ,  G06F12/1036 ,  G06F12/10

Abstract: A virtual-to-virtual page table maps a main surface containing the actual data and a metadata or auxiliary surface that gives information about compression of the main surface. In order to access the metadata that corresponds to main surface, an additional virtual-to-virtual table may be used ahead of the regular page table mapping to avoid the need to pass the metadata base address and x, y coordinates across a pipeline which may result in multiple memory writes.

公开(公告)号：US20180300928A1

公开(公告)日：2018-10-18

申请号：US15488543

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Niranjan L. Cooray ,  Abhishek R. Appu

IPC: G06T15/00

CPC classification number: G06F12/00

Abstract: An apparatus to facilitate guaranteed forward progress for graphics data is disclosed. The apparatus includes a plurality of ports to receive and transmit streams of graphics data, one or more buffers associated with each of the plurality of ports to store the graphics data and switching logic to virtually partition each of the one or more buffers to allocate a dedicated buffer to receive each of a plurality of independent streams of graphics data.

公开(公告)号：US20220075746A1

公开(公告)日：2022-03-10

申请号：US17014023

申请日：2020-09-08

Applicant: Intel Corporation

Inventor： Hema Chand Nalluri ,  Ankur Shah ,  Joydeep Ray ,  Aditya Navale ,  Altug Koker ,  Murali Ramadoss ,  Niranjan L. Cooray ,  Jeffery S. Boles ,  Aravindh Anantaraman ,  David Puffer ,  James Valerio ,  Vasanth Ranganathan

IPC: G06F13/40 ,  G06F13/16 ,  G06F9/30 ,  G06F9/52 ,  G06F12/0837 ,  G06F12/0888

Abstract: An apparatus to facilitate memory barriers is disclosed. The apparatus comprises an interconnect, a device memory, a plurality of processing resources, coupled to the device memory, to execute a plurality of execution threads as memory data producers and memory data consumers to a device memory and a system memory and fence hardware to generate fence operations to enforce data ordering on memory operations issued to the device memory and a system memory coupled via the interconnect.

公开(公告)号：US10891773B2

公开(公告)日：2021-01-12

申请号：US15482677

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Pattabhiraman K ,  Balaji Vembu ,  Altug Koker ,  Niranjan L. Cooray ,  Josh B. Mastronarde

IPC: G06T15/00 ,  G06F9/455 ,  G06T1/60 ,  G09G5/36 ,  G09G5/00 ,  G09G5/393 ,  G06F9/48 ,  G06F9/50 ,  G06T15/04 ,  G06T15/80 ,  G06T17/10 ,  G06T17/20

Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

公开(公告)号：US10860468B2

公开(公告)日：2020-12-08

申请号：US16379137

申请日：2019-04-09

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Niranjan L. Cooray ,  Abhishek R. Appu

IPC: G06F12/00 ,  G06F12/0875 ,  G06F9/54 ,  G06T1/60 ,  G06F12/0811

Abstract: An apparatus to facilitate guaranteed forward progress for graphics data is disclosed. The apparatus includes a plurality of ports to receive and transmit streams of graphics data, one or more buffers associated with each of the plurality of ports to store the graphics data and switching logic to virtually partition each of the one or more buffers to allocate a dedicated buffer to receive each of a plurality of independent streams of graphics data.

公开(公告)号：US10802970B1

公开(公告)日：2020-10-13

申请号：US16366266

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Altug Koker ,  Vidhya Krishnan ,  Ronald W. Silvas ,  John H. Feit ,  Prasoonkumar Surti ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F12/0837 ,  G06F9/38 ,  G06F16/907 ,  H04L9/06 ,  G06F12/0811

Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.

公开(公告)号：US10380039B2

公开(公告)日：2019-08-13

申请号：US15482690

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Satyeshwar Singh ,  Sameer KP ,  Ankur N. Shah ,  Kun Tian ,  Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  Pattabhiraman K ,  David Puffer ,  David J. Cowperthwaite ,  Rajesh M. Sankaran

IPC: G06F12/109 ,  G06F11/07 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20190213140A1

公开(公告)日：2019-07-11

申请号：US15863347

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Altug Koker ,  Nicolas Kacevas ,  Parth S. Damani ,  David Standring

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/652 ,  G06F2212/68

Abstract: An apparatus to facilitate page translation is disclosed. The apparatus a set associative translation lookaside buffer (TLB) including a plurality of entries to store virtual to physical memory address translations and a page size table (PST) including a plurality of entries to store page size corresponding to each of the TLB entries.

公开(公告)号：US11416402B2

公开(公告)日：2022-08-16

申请号：US17068742

申请日：2020-10-12

Applicant: Intel Corporation

Inventor： Niranjan L. Cooray ,  Altug Koker ,  Vidhya Krishnan ,  Ronald W. Silvas ,  John H. Feit ,  Prasoonkumar Surti ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06F12/0837 ,  G06F9/38 ,  G06F16/907 ,  H04L9/06 ,  G06F12/0811

Abstract: Embodiments described herein provide an apparatus comprising a processor to allocate a first memory space for data for a graphics workload, the first memory comprising a first plurality of addressable memory locations, allocate a second memory space for compression metadata relating to the data for the graphics workload, the second memory space comprising a second plurality of addressable memory locations and having an amount of memory corresponding to a predetermined ratio of the amount of memory allocated to first memory space, and configure a direct memory mapping between the first plurality of addressable memory locations and the second plurality of addressable memory locations. Other embodiments may be described and claimed.

公开(公告)号：US11023998B2

公开(公告)日：2021-06-01

申请号：US16373477

申请日：2019-04-02

Applicant: Intel Corporation

Inventor： Nicolas Kacevas ,  Niranjan L. Cooray ,  Madhura Joshi ,  Satyanarayana Nekkalapu

IPC: G06F9/48 ,  G06T1/60 ,  G06F12/1027 ,  G09G5/36 ,  G06T15/00 ,  G09G3/00

Abstract: An apparatus is provided which comprises: a first engine buffer to receive a first engine request; a first engine register coupled to the first engine buffer, wherein the first engine register is to store first engine credits associated with the first engine buffer; a second engine buffer to receive a second engine request; a second engine register coupled to the second engine buffer, wherein the second engine register is to store second engine credits associated with the second engine buffer; and a common buffer which is common to the first and second engines, wherein the first engine credits represents one or more slots in the common buffer for servicing the first engine request for access to a common resource, and wherein the second engine credits represents one or more slots in the common buffer for servicing the second engine request for access to the common resource.