公开(公告)号：US08799566B2

公开(公告)日：2014-08-05

申请号：US12963797

申请日：2010-12-09

申请人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

发明人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

IPC分类号： G06F12/00 ,  G11C7/00

CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4065

摘要： A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.

摘要翻译： 一种具有可编程刷新周期的存储器系统，包括存储器件，该存储器件包括与存储器阵列和存储器控制器通信的存储器单元的存储器阵列和刷新电路。 刷新电路被配置为响应于接收到刷新命令从存储器控制器接收刷新命令并且用于刷新存储器件中的多个存储器单元。 响应于接收刷新命令刷新的存储器单元的数量是可编程的。

公开(公告)号：US08359521B2

公开(公告)日：2013-01-22

申请号：US12018030

申请日：2008-01-22

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G06F11/1004

摘要： A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.

摘要翻译： 一种用于提供具有共享错误反馈引脚的存储器件的系统和方法。 该系统包括具有被配置为接收数据比特和CRC比特，CRC接收电路，CRC创建电路，存储器装置垫和驱动器电路的数据接口的存储器装置。 CRC接收电路利用CRC方程来检测一个或多个接收数据和接收的CRC比特中的错误。 CRC创建电路利用CRC方程来创建与要发送到单独设备位的数据一致的CRC位。 存储器件焊盘被配置为报告在接收的数据和接收的CRC位中检测到的任何错误。 驱动器电路连接到存储器件焊盘并与驻留在一个或多个其它存储器件上的一个或多个其它驱动器电路合并到错误报告行中。

公开(公告)号：US08023358B2

公开(公告)日：2011-09-20

申请号：US12061045

申请日：2008-04-02

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Warren E. Maule ,  Kenneth L. Wright

IPC分类号： G11C8/00

CPC分类号： G11C5/00 ,  G11C7/1018

摘要： A memory system, memory interface device and method for a non-power-of-two burst length are provided. The memory system includes a plurality of memory devices with non-power-of-two burst length logic and a memory interface device including non-power-of-two burst length generation logic. The non-power-of-two burst length generation logic extends a burst length from a power-of-two value to insert an error-detecting code in a burst on data lines between the memory interface device and the plurality of memory devices.

摘要翻译： 提供了一种用于非二次突发长度的存储器系统，存储器接口装置和方法。 存储器系统包括具有非二次突发长度逻辑的多个存储器件和包括非二次突发长度生成逻辑的存储器接口器件。 非功率二突发长度生成逻辑从两个功率值扩展突发长度，以将错误检测码插入到存储器接口设备和多个存储器件之间的数据线上的突发中。

公开(公告)号：US20110199843A1

公开(公告)日：2011-08-18

申请号：US12705674

申请日：2010-02-15

申请人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

发明人： Daniel M. Dreps ,  Kevin C. Gower ,  Michael K. Kerr ,  Kyu-hyoun Kim ,  David W. Mann ,  James A. Mossman ,  Michael A. Sorna ,  Robert B. Tremaine ,  William M. Zevin

IPC分类号： G11C7/00

CPC分类号： G06F13/4243 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C2207/2254

摘要： A method and apparatus for determining correct timing for receiving, in a host in a memory system, of a normal toggle transmitted by an addressed memory chip on a bidirectional data strobe. An offset in the data strobe is established, either by commanding the addressed memory chip, in a training period, to drive the data strobe to a known state, except during transmission of a normal toggle, or by providing a voltage offset between a true and a complement phase in the data strobe, or by providing a circuit bias in a differential receiver on the host the receives the data strobe. A series of read commands are transmitted by the host to the addressed memory chip, which responds by transmitting the normal toggle. Timing of reception of the normal toggle as received by the host chip is adjusted until the normal toggle is correctly received.

摘要翻译： 一种用于确定正确定时的方法和装置，用于在存储器系统中的主机中接收在双向数据选通信号上由寻址的存储器芯片发送的正常触发。 通过在训练期间命令寻址的存储器芯片来建立数据选通中的偏移量，以将数据选通驱动到已知状态，除了在正常触发的传输期间，或通过在真实和 数据选通中的补码相位，或通过在主机上的差分接收器中提供电路偏置来接收数据选通信号。 一系列读命令由主机发送到寻址的存储器芯片，通过发送普通切换进行响应。 调整由主机芯片接收到的正常切换的接收定时，直到正常接通正常。

公开(公告)号：US07952944B2

公开(公告)日：2011-05-31

申请号：US12112391

申请日：2008-04-30

申请人： Kyu-hyoun Kim ,  Paul W. Coteus

发明人： Kyu-hyoun Kim ,  Paul W. Coteus

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/1048 ,  G11C7/109 ,  H04L25/0298

摘要： A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT is in communication with the control bus connector, and the ODT provides a level of termination resistance to a control bus connected to the control bus connector. The mechanism latches data received via the data bus connectors in response to a signal received via one or both of the load signal connector and the reset signal connector. The data is utilized to set the level of termination resistance provided by the ODT.

摘要翻译： 一种用于提供控制信号总线的管芯端接（ODT）的系统。 该系统包括存储器件，其包括多个数据总线连接器，负载信号连接器和复位信号连接器中的一个或两个，控制总线连接器，ODT和机构。 ODT与控制总线连接器通信，ODT为连接到控制总线连接器的控制总线提供一定程度的终端电阻。 该机构响应于经由一个或两个负载信号连接器和复位信号连接器接收到的信号，锁存经由数据总线连接器接收的数据。 该数据用于设置由ODT提供的终端电阻的电平。

公开(公告)号：US20090327800A1

公开(公告)日：2009-12-31

申请号：US12107908

申请日：2008-04-23

申请人： Kyu-hyoun Kim

发明人： Kyu-hyoun Kim

IPC分类号： G06F11/20

CPC分类号： G06F11/1044 ,  G11C2029/0411

摘要： An apparatus, system, and method for providing error protection for data-masking bits in a memory device of a memory system are provided. The memory device includes a memory core to store data, and a data interface to receive the data and data-masking bits associated with a write command. The memory device also includes a gating block to control writing the data to the memory core, where the writing of the data to the memory core is inhibited upon detecting an error with one or more of the data-masking bits.

摘要翻译： 提供了一种用于为存储器系统的存储器件中的数据屏蔽位提供错误保护的装置，系统和方法。 存储器件包括用于存储数据的存储器核心和用于接收与写入命令相关联的数据和数据掩蔽位的数据接口。 存储器件还包括一个门控块，用于控制将数据写入存储器核心，其中在检测到一个或多个数据掩蔽位的错误时，将数据写入存储器核心被禁止。

公开(公告)号：US20090273960A1

公开(公告)日：2009-11-05

申请号：US12112391

申请日：2008-04-30

申请人： Kyu-hyoun Kim ,  Paul W. Coteus

发明人： Kyu-hyoun Kim ,  Paul W. Coteus

IPC分类号： G11C5/02 ,  G11C7/00 ,  H03K19/003

CPC分类号： G11C7/1078 ,  G11C7/1048 ,  G11C7/109 ,  H04L25/0298

摘要： A system for providing on-die termination (ODT) of a control signal bus. The system includes a memory device that includes a plurality of data bus connectors, one or both of a load signal connector and a reset signal connector, a control bus connector, an ODT, and a mechanism. The ODT is in communication with the control bus connector, and the ODT provides a level of termination resistance to a control bus connected to the control bus connector. The mechanism latches data received via the data bus connectors in response to a signal received via one or both of the load signal connector and the reset signal connector. The data is utilized to set the level of termination resistance provided by the ODT.

摘要翻译： 一种用于提供控制信号总线的管芯端接（ODT）的系统。 该系统包括存储器件，其包括多个数据总线连接器，负载信号连接器和复位信号连接器中的一个或两个，控制总线连接器，ODT和机构。 ODT与控制总线连接器通信，ODT为连接到控制总线连接器的控制总线提供一定程度的终端电阻。 该机构响应于经由一个或两个负载信号连接器和复位信号连接器接收到的信号，锁存经由数据总线连接器接收的数据。 该数据用于设置由ODT提供的终端电阻的电平。

公开(公告)号：US07612621B2

公开(公告)日：2009-11-03

申请号：US11749409

申请日：2007-05-16

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Daniel M. Dreps

IPC分类号： H03B27/00

CPC分类号： H03K5/151 ,  H03K5/13 ,  H03K2005/00052 ,  H03K2005/00234

摘要： A system for providing open-loop quadrature clock generation. The system is implemented by a ring oscillator structure that includes input inverters for receiving an input clock, forward direction loop inverters, backward direction loop inverters, one or more outputs, and cross-coupled latches connected between any two opposite nodes.

摘要翻译： 一种用于提供开环正交时钟生成的系统。 该系统由环形振荡器结构实现，该环形振荡器结构包括用于接收输入时钟的输入反相器，正向环路逆变器，反向环路逆变器，一个或多个输出以及连接在任何两个相对节点之间的交叉耦合的锁存器。

公开(公告)号：US07567106B2

公开(公告)日：2009-07-28

申请号：US11496447

申请日：2006-08-01

申请人： Moon-sook Park ,  Kyu-hyoun Kim

发明人： Moon-sook Park ,  Kyu-hyoun Kim

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K2005/00052 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/0891

摘要： A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.

摘要翻译： 一种产生时钟信号的半导体器件和方法，其中锁相环（PLL）或延迟锁环（DLL）包括具有共享电荷泵和多个放大部分的占空比校正电路（DCC）。 多个放大部分产生内部时钟信号。 共享电荷泵响应于内部时钟信号调节控制信号（VC）的电压电平，并向每个放大部分提供控制信号VC。

公开(公告)号：US20090187794A1

公开(公告)日：2009-07-23

申请号：US12018030

申请日：2008-01-22

申请人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

发明人： Kyu-hyoun Kim ,  Paul W. Coteus ,  Timothy J. Dell

IPC分类号： G06F11/00

CPC分类号： G06F11/1004

摘要： A system and method for providing a memory device having a shared error feedback pin. The system includes a memory device having a data interface configured to receive data bits and CRC bits, CRC receiving circuitry, CRC creation circuitry, a memory device pad, and driver circuitry. The CRC receiving circuitry utilizes a CRC equation for the detection of errors in one or more of the received data and the received CRC bits. The CRC creation circuitry utilizes the CRC equation for the creation of CRC bits consistent with data to be transmitted to a separate device bits. The memory device pad is configured for reporting of any errors detected in the received data and the received CRC bits. The driver circuitry is connected to the memory device pad and merged with one or more other driver circuitries resident on one or more other memory devices into an error reporting line.

摘要翻译： 一种用于提供具有共享错误反馈引脚的存储器件的系统和方法。 该系统包括具有被配置为接收数据比特和CRC比特，CRC接收电路，CRC创建电路，存储器装置垫和驱动器电路的数据接口的存储器装置。 CRC接收电路利用CRC方程来检测一个或多个接收数据和接收的CRC比特中的错误。 CRC创建电路利用CRC方程来创建与要发送到单独设备位的数据一致的CRC位。 存储器件焊盘被配置为报告在接收的数据和接收的CRC位中检测到的任何错误。 驱动器电路连接到存储器件焊盘并与驻留在一个或多个其它存储器件上的一个或多个其它驱动器电路合并到错误报告行中。