公开(公告)号：US20170249163A1

公开(公告)日：2017-08-31

申请号：US15273398

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/44 ,  G06F13/42 ,  G06F1/24 ,  G06F9/445

Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

公开(公告)号：US20170249098A1

公开(公告)日：2017-08-31

申请号：US15273432

申请日：2016-09-22

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Haining Zhang ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F3/06 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F1/24 ,  G06F3/0626 ,  G06F3/0637 ,  G06F3/0665 ,  G06F3/0683 ,  G06F8/63 ,  G06F12/1441 ,  G06F13/4282 ,  G06F2212/1008 ,  G06F2212/1052 ,  G06F2212/1056 ,  G06F2212/621 ,  G06F2213/0026

Abstract: Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.

公开(公告)号：US20160103743A1

公开(公告)日：2016-04-14

申请号：US14879030

申请日：2015-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F11/14

CPC classification number: G06F1/3293 ,  G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F11/1417 ,  G06F11/1471 ,  G06F11/1474 ,  G06F13/4282 ,  G06F2201/805 ,  G06F2201/87 ,  Y02D10/122 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/152 ,  Y02D10/171

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

Abstract translation: 两个（或多个）可独立操作的处理器之间的处理器间通信（IPC）链接的方法和装置。 在一个方面，IPC协议基于用于运行时处理的“共享”存储器接口（即，独立可操作的处理器每个共享（虚拟或物理上）公共存储器接口）。 在另一方面，IPC通信链路被配置为支持在引导序列期间使用的主机驱动的引导协议，以在外围设备和主处理器之间建立基本通信路径。 本文描述的各种其他实施例包括睡眠过程（如针对主机和外围处理器分别定义的）和错误处理。

公开(公告)号：US11381514B2

公开(公告)日：2022-07-05

申请号：US15973153

申请日：2018-05-07

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Cahya Adiansyah Masputra

IPC: H04L47/62 ,  H04L45/30

Abstract: Methods and apparatus for non-sequential packet transfer. Prior art multi-processor devices implement a complete network communications stack at each processor. The disclosed embodiments provide techniques for delivering network layer (L3) and/or transport layer (L4) data payloads in the order of receipt, rather than according to the data link layer (L2) order. The described techniques enable e.g., earlier packet delivery. Such design topologies can operate within a substantially smaller memory footprint compared to prior art solutions. As a related benefit, applications that are unaffected by data link layer corruptions can receive data immediately (rather than waiting for the re-transmission of an unrelated L4 data flow) and thus the overall network latency can be greatly reduced and user experience can be improved.

公开(公告)号：US11178259B2

公开(公告)日：2021-11-16

申请号：US16146533

申请日：2018-09-28

Applicant: Apple Inc.

Inventor： Cahya Adiansyah Masputra ,  Sandeep Nair ,  Karan Sanghi ,  Mingzhe Zhang ,  Jason McElrath

IPC: H04L29/06 ,  H04L12/46 ,  G06F9/54 ,  G06F9/48 ,  G06F9/50 ,  G06F12/10 ,  G06F13/16 ,  G06F3/06 ,  G06F9/46 ,  G06F12/02 ,  H04L12/859 ,  H04L12/851 ,  H04L12/863 ,  H04L12/935 ,  H04L12/861 ,  G06F9/455 ,  H04L12/801 ,  H04L12/841 ,  G06F9/52 ,  H04L12/26 ,  G06F16/23 ,  G06F21/52 ,  H04L12/833 ,  H04L12/835 ,  H04L12/823 ,  H04L12/865 ,  G06F21/56 ,  G06F16/22 ,  H04L29/12 ,  H04L29/08 ,  H04L1/00

Abstract: Methods and apparatus for efficient data transfer within a user space network stack. Unlike prior art monolithic networking stacks, the exemplary networking stack architecture described hereinafter includes various components that span multiple domains (both in-kernel, and non-kernel). For example, unlike traditional “socket” based communication, disclosed embodiments can transfer data directly between the kernel and user space domains. Direct transfer reduces the per-byte and per-packet costs relative to socket based communication. A user space networking stack is disclosed that enables extensible, cross-platform-capable, user space control of the networking protocol stack functionality. The user space networking stack facilitates tighter integration between the protocol layers (including TLS) and the application or daemon. Exemplary systems can support multiple networking protocol stack instances (including an in-kernel traditional network stack).

公开(公告)号：US20210041908A1

公开(公告)日：2021-02-11

申请号：US17066321

申请日：2020-10-08

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F1/12 ,  G06F1/324

Abstract: Methods and apparatus for synchronization of time between independently operable processors. Time synchronization between independently operable processors is complicated by a variety of factors. For example, neither independently operable processor controls the other processor's task scheduling, power, or clocking. In one exemplary embodiment, a processor can initiates a time synchronization process by disabling power state machines and transacting timestamps for a commonly observed event. In one such embodiment, timestamps may be transferred via inter-processor communication (IPC) mechanisms (e.g., transfer descriptors (TDs), and completion descriptors (CDs)). Both processors may thereafter coordinate in time synchronization efforts (e.g., speeding up or slowing down their respective clocks, etc.).

公开(公告)号：US20210011785A1

公开(公告)日：2021-01-14

申请号：US17035499

申请日：2020-09-28

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F9/46

Abstract: Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.

公开(公告)号：US10853272B2

公开(公告)日：2020-12-01

申请号：US16259543

申请日：2019-01-28

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US20200348989A1

公开(公告)日：2020-11-05

申请号：US16933826

申请日：2020-07-20

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F15/173 ,  G06F9/38

Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.

公开(公告)号：US10775871B2

公开(公告)日：2020-09-15

申请号：US15647063

申请日：2017-07-11

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Richard Solotke

IPC: G06F1/3287 ,  G06F9/4401

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.