公开(公告)号：US07941728B2

公开(公告)日：2011-05-10

申请号：US11683285

申请日：2007-03-07

申请人： Philip George Emma ,  Wing K. Luk ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

发明人： Philip George Emma ,  Wing K. Luk ,  Thomas R. Puzak ,  Vijayalakshmi Srinivasan

IPC分类号： H03M13/00

CPC分类号： G06F12/0802 ,  G06F11/1064 ,  G06F11/1666

摘要： A system and method of providing a cache system having a store-in policy and affording the advantages of store-in cache operation, while simultaneously providing protection against soft-errors in locally modified data, which would normally preclude the use of a store-in cache when reliability is paramount. The improved store-in cache mechanism includes a store-in L1 cache, at least one higher-level storage hierarchy; an ancillary store-only cache (ASOC) that holds most recently stored-to lines of the store-in L1 cache, and a cache controller that controls storing of data to the ancillary store-only cache (ASOC) and recovering of data from the ancillary store-only cache (ASOC) such that the data from the ancillary store-only cache (ASOC) is used only if parity errors are encountered in the store-in L1 cache.

摘要翻译： 提供具有存储策略并提供存储高速缓存操作的优点的缓存系统的系统和方法，同时提供对本地修改的数据中的软错误的保护，这通常会阻止使用存储 缓存当可靠性至关重要时。 改进的存储高速缓存机制包括存储L1高速缓存，至少一个更高级别的存储层级; 保存最近存储在L1高速缓存中的行的辅助存储专用缓存（ASOC）以及控制将数据存储到辅助存储高速缓存（ASOC）并从 辅助存储高速缓存（ASOC），使得只有在存储的L1高速缓存中遇到奇偶校验错误时才使用来自辅助存储高速缓存（ASOC）的数据。

公开(公告)号：US07930578B2

公开(公告)日：2011-04-19

申请号：US11862559

申请日：2007-09-27

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Zhigang Hu ,  Hans Jacobson ,  Prabhakar N. Kudva ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Chen-Yong Cher ,  Zhigang Hu ,  Hans Jacobson ,  Prabhakar N. Kudva ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

IPC分类号： G06F1/00 ,  G06F11/30 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/206 ,  G06F9/3836 ,  G06F9/3869 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D50/20

摘要： A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor inputs and command state vector inputs, determining, at first periodic time intervals, a current performance level, a current power consumption level and an assigned power budget for the system based on the utilization sensor inputs and the command state vector inputs, and determining, at second periodic time intervals, a token re-allocation map based on the current performance level, the current power consumption level and the assigned power budget for the system, according to a re-assigned power budget of at least one of the connected components, while enforcing a power consumption limit based on a total number of allocated tokens in the system.

摘要翻译： 一种连接组件的系统的电源管理方法包括：在所连接的组件之间初始化令牌分配映射，其中每个组件被分配由令牌分配映射中的分配的令牌数量确定的功率预算，监视利用率传感器输入和命令 状态向量输入，基于所述利用传感器输入和所述命令状态向量输入，以第一周期性时间间隔确定所述系统的当前性能水平，当前功耗级别和所分配的功率预算，以及在所述第二周期时间 间隔，基于当前性能水平的令牌重新分配图，当前功耗水平和系统的分配的功率预算，根据至少一个连接的组件的重新分配的功率预算，同时执行功率 基于系统中分配的令牌总数的消耗限制。

公开(公告)号：US20090193187A1

公开(公告)日：2009-07-30

申请号：US12103290

申请日：2008-04-15

申请人： John E. Barth, Jr. ,  Philip G. Emma ,  Hillery C. Hunter ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

发明人： John E. Barth, Jr. ,  Philip G. Emma ,  Hillery C. Hunter ,  Vijayalakshmi Srinivasan ,  Arnold S. Tran

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/1028 ,  Y02D10/13

摘要： A design structure for an embedded DRAM (eDRAM) having multi-use refresh cycles is described. In one embodiment, there is a multi-level cache memory system that comprises a pending write queue configured to receive pending prefetch operations from at least one of the levels of cache. A prefetch queue is configured to receive prefetch operations for at least one of the levels of cache. A refresh controller is configured to determine addresses within each level of cache that are due for a refresh. The refresh controller is configured to assert a refresh write-in signal to write data supplied from the pending write queue specified for an address due for a refresh rather than refresh existing data. The refresh controller asserts the refresh write-in signal in response to a determination that there is pending data to supply to the address specified to have the refresh. The refresh controller is further configured to assert a refresh read-out signal to send refreshed data to the prefetch queue of a higher level of cache as a prefetch operation in response to a determination that the refreshed data is useful.

摘要翻译： 描述了具有多次使用刷新周期的嵌入式DRAM（eDRAM）的设计结构。 在一个实施例中，存在多级高速缓冲存储器系统，其包括被配置为从高速缓存的至少一个级别接收未决的预取操作的等待写入队列。 预取队列被配置为接收至少一个缓存级别的预取操作。 刷新控制器被配置为确定要刷新到期的每个高速缓存级别内的地址。 刷新控制器被配置为断言刷新写入信号以写入从针对刷新而不是刷新现有数据的地址指定的等待写入队列提供的数据。 刷新控制器响应于确定有未决数据提供给被指定为刷新的地址，来确定刷新写入信号。 刷新控制器还被配置为响应于确定刷新的数据是有用的，将更新读出信号断言以将更新的数据发送到较高级别的高速缓存的预取队列作为预取操作。

公开(公告)号：US07516310B2

公开(公告)日：2009-04-07

申请号：US11422996

申请日：2006-06-08

申请人： Erik R. Altman ,  Vijayalakshmi Srinivasan

发明人： Erik R. Altman ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/00

CPC分类号： G06F9/3851 ,  G06F9/383 ,  G06F9/3834 ,  G06F12/0842 ,  Y02D10/13

摘要： A method for reducing the number of times in-flight loads must be searched by store instructions in a multi-threaded processor. A load issue for a thread t_old is frozen for a number of cycles. A t13 new load instruction is rejected. A notification is sent to the rest of the processor that the t_new load instruction has been rejected. A load reorder queue (LRQ) of a t_old is snooped for any load which comes from a cache line L accessed by the load instruction and then forces such loads to be re-executed. Ownership of line L is changed to thread t_new.

摘要翻译： 必须通过存储指令在多线程处理器中搜索减少飞行载荷次数的方法。 线程t_old的加载问题会冻结多个周期。 t13新加载指令被拒绝。 发送处理器的其余部分通知t_new加载指令已被拒绝。 对于来自由加载指令访问的高速缓存行L的任何负载，并监视t_old的加载重新排序队列（LRQ），然后强制重新执行此类负载。 线L的所有权更改为线程t_new。

公开(公告)号：US20090083492A1

公开(公告)日：2009-03-26

申请号：US12272612

申请日：2008-11-17

申请人： Alper Buyuktosunoglu ,  Zhigang Hu ,  Jude A. Rivers ,  John T. Robinson ,  Xiaowei Shen ,  Vijayalakshmi Srinivasan

发明人： Alper Buyuktosunoglu ,  Zhigang Hu ,  Jude A. Rivers ,  John T. Robinson ,  Xiaowei Shen ,  Vijayalakshmi Srinivasan

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0897 ,  G06F12/128 ,  Y02D10/13

摘要： A hardware based method for determining when to migrate cache lines to the cache bank closest to the requesting processor to avoid remote access penalty for future requests. In a preferred embodiment, decay counters are enhanced and used in determining the cost of retaining a line as opposed to replacing it while not losing the data. In one embodiment, a minimization of off-chip communication is sought; this may be particularly useful in a CMP environment.

摘要翻译： 一种基于硬件的方法，用于确定何时将高速缓存行迁移到最靠近请求处理器的缓存库，以避免对未来请求的远程访问损失。 在优选实施例中，衰减计数器被增强并用于确定保留线的成本，而不是在不丢失数据的情况下替换它。 在一个实施例中，寻求片外通信的最小化; 这可能在CMP环境中特别有用。

公开(公告)号：US07447923B2

公开(公告)日：2008-11-04

申请号：US11207333

申请日：2005-08-19

申请人： Pradip Bose ,  Alper Buyuktosunoglu ,  Zhigang Hu ,  Hans Mikael Jacobson ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Zhigang Hu ,  Hans Mikael Jacobson ,  Vijayalakshmi Srinivasan ,  Victor Zyuban

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/30145 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3867 ,  Y02D10/171 ,  Y02D10/24

摘要： A device for controlling power parameters in a microprocessor includes a resource activation control unit for controlling the maximum power of the microprocessor and two or more resources. The resource activation control unit controls the activation of the resources such that the consumed and dissipated power of the microprocessor does not exceed a power bound which is configurable to a predetermined value below the maximum power.

摘要翻译： 用于控制微处理器中的功率参数的装置包括用于控制微处理器的最大功率和两个或更多个资源的资源激活控制单元。 资源激活控制单元控制资源的激活，使得微处理器的消耗和耗散功率不超过可配置为低于最大功率的预定值的功率限制。

公开(公告)号：US20080270702A1

公开(公告)日：2008-10-30

申请号：US12131418

申请日：2008-06-02

申请人： Galen A. Rasche ,  Jude A. Rivers ,  Vijayalakshmi Srinivasan

发明人： Galen A. Rasche ,  Jude A. Rivers ,  Vijayalakshmi Srinivasan

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/6022

摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.

公开(公告)号：US07366875B2

公开(公告)日：2008-04-29

申请号：US11069014

申请日：2005-03-01

申请人： Galen A. Rasche ,  Jude A. Rivers ,  Vijayalakshmi Srinivasan

发明人： Galen A. Rasche ,  Jude A. Rivers ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/30

CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/6022

摘要： A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency of these traces is reduced.

摘要翻译： 一种新颖的跟踪缓存设计和组织来高效地存储和检索多路径跟踪。 目标是设计跟踪缓存，其能够存储多路径跟踪，而不会在跟踪中显着重复。 此外，这些迹线的有效访问延迟减少了。

公开(公告)号：US07337271B2

公开(公告)日：2008-02-26

申请号：US10724815

申请日：2003-12-01

申请人： Philip George Emma ,  Allan Mark Hartstein ,  Brian R. Prasky ,  Thomas Roberts Puzak ,  Moinuddin Khalil Ahmed Qureshi ,  Vijayalakshmi Srinivasan

发明人： Philip George Emma ,  Allan Mark Hartstein ,  Brian R. Prasky ,  Thomas Roberts Puzak ,  Moinuddin Khalil Ahmed Qureshi ,  Vijayalakshmi Srinivasan

IPC分类号： G06F12/00 ,  G06F9/00

CPC分类号： G06F9/3806

摘要： A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.

摘要翻译： 存储器存储结构包括存储器存储设备和具有第一大小并以第一速度操作的第一元结构。 基于存储在存储器中的信息，第一速度比用于存储元信息的第二速度快。 第二个元结构与第一个元结构分层关联。 第二元结构具有大于第一尺寸的第二尺寸并且以第二速度操作，使得通过第一和第二元结构的共同作用来提供更快更准确的预取。 提供了一种用于在第一元结构中组装元信息并将该信息复制到第二元结构的方法，并且将其从第二元结构预取存储到其使用之前的第一元结构。

公开(公告)号：US20080046703A1

公开(公告)日：2008-02-21

申请号：US11923902

申请日：2007-10-25

申请人： Philip Emma ,  Allan Hartstein ,  Brian Prasky ,  Thomas Puzak ,  Moinuddin Ahmed Qureshi ,  Vijayalakshmi Srinivasan

发明人： Philip Emma ,  Allan Hartstein ,  Brian Prasky ,  Thomas Puzak ,  Moinuddin Ahmed Qureshi ,  Vijayalakshmi Srinivasan

IPC分类号： G06F9/00

CPC分类号： G06F9/3806

摘要： A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second meta-structure is hierarchically associated with the first meta-structure. The second meta-structure has a second size larger than the first size and operates at the second speed such that faster and more accurate prefetching is provided by coaction of the first and second meta-structures. A method is provided to assemble the meta-information in the first meta-structure and copy this information to the second meta-structure, and prefetching the stored information from the second meta-structure to the first meta-structure ahead of its use.

摘要翻译： 存储器存储结构包括存储器存储设备和具有第一大小并以第一速度操作的第一元结构。 基于存储在存储器中的信息，第一速度比用于存储元信息的第二速度快。 第二个元结构与第一个元结构分层关联。 第二元结构具有大于第一尺寸的第二尺寸并且以第二速度操作，使得通过第一和第二元结构的共同作用来提供更快更准确的预取。 提供了一种用于在第一元结构中组装元信息并将该信息复制到第二元结构的方法，并且将其从第二元结构预取存储到其使用之前的第一元结构。