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57 条记录 (耗时 0.022 秒)

    Adaptive multi-bit error correction in endurance limited memories
    7.
    发明授权
    Adaptive multi-bit error correction in endurance limited memories 失效
    耐力有限的存储器中的自适应多位错误校正

    公开(公告)号：US08589762B2

    公开(公告)日：2013-11-19

    申请号：US13176092

    申请日：2011-07-05

    申请人： Jude A. Rivers ,  Vijayalakshmi Srinivasan

    发明人： Jude A. Rivers ,  Vijayalakshmi Srinivasan

    IPC分类号： G11C29/00

    CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C16/3418 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.

    摘要翻译： 可以通过自适应多位错误校正方法来实现多位卡滞故障恢复，其中降低了纠错硬件的开销，而不影响存储器件的使用寿命。 纠错逻辑硬件与存储器块分离。 错误校正逻辑块被分区，使得纠错逻辑条目基于在不同存储器块中出现不同数量的错误的概率来支持不同数量的纠错能力。 错误的存储器块被映射到适当的纠错逻辑条目。 取决于实施例，映射可以是一对一或多对一。 错误校正逻辑条目的自适应分割可以被配置为匹配逻辑块中的误差的预计统计分布，并且可以减少总误差校正逻辑开销，提供足够的纠错和/或延长存储器件的寿命。

    ADAPTIVE MULTI-BIT ERROR CORRECTION IN ENDURANCE LIMITED MEMORIES
    8.
    发明申请
    ADAPTIVE MULTI-BIT ERROR CORRECTION IN ENDURANCE LIMITED MEMORIES 失效
    自适应多重错误修正在有限的记忆

    公开(公告)号：US20130013977A1

    公开(公告)日：2013-01-10

    申请号：US13176092

    申请日：2011-07-05

    申请人： Jude A. Rivers ,  Vijayalakshmi Srinivasan

    发明人： Jude A. Rivers ,  Vijayalakshmi Srinivasan

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C16/3418 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/0411

    摘要： Multi-bit stuck-at fault error recovery can be enabled by adaptive multi-bit error correction method, in which the overhead of error correction hardware is reduced without affecting the lifetime of the memory device. Error correction logic hardware is decoupled from memory blocks. An error correction logic block is partitioned such that error correction logic entries support different number of error correction capabilities based on the probability of occurrence of the different number of errors in different memory blocks. Faulty memory blocks are mapped to appropriate error correction logic entries. The mapping can be one-to-one or many-to-one depending on embodiments. The adaptive partitioning of the error correction logic entries can be configured to match projected statistical distribution of errors in logic blocks, and can reduce the total error correction logic overhead, provide sufficient error correction, and/or extend the lifetime of the memory device.

    摘要翻译： 可以通过自适应多位错误校正方法来实现多位卡滞故障恢复，其中降低了纠错硬件的开销，而不影响存储器件的使用寿命。 纠错逻辑硬件与存储器块分离。 错误校正逻辑块被分区，使得纠错逻辑条目基于在不同存储器块中出现不同数量的错误的概率来支持不同数量的纠错能力。 错误的存储器块被映射到适当的纠错逻辑条目。 取决于实施例，映射可以是一对一或多对一。 错误校正逻辑条目的自适应分割可以被配置为匹配逻辑块中的误差的预测统计分布，并且可以减少总误差校正逻辑开销，提供足够的纠错和/或延长存储器件的寿命。

    Enhanced modularity in heterogeneous 3D stacks
    10.
    发明授权
    Enhanced modularity in heterogeneous 3D stacks 有权
    在异构3D堆栈中增强模块化

    公开(公告)号：US09373557B2

    公开(公告)日：2016-06-21

    申请号：US13535675

    申请日：2012-06-28

    申请人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

    发明人： Philip G. Emma ,  Eren Kursun ,  Jude A. Rivers

    IPC分类号： G06F17/50 ,  H01L23/14 ,  H05K3/46 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H05K3/30 ,  H01L21/48

    CPC分类号： H01L23/147 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/5382 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/30 ,  H05K3/465 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49137 ,  Y10T29/49146 ,  H01L2924/00

    摘要： A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to a layer in the 3D computer processing chip stack plan. The method also includes identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The method further includes determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment generates and integrates both the layer including the common structures and technologies and the host layer including the uncommon structures and technologies to form the 3D computer processing chip stack.

    摘要翻译： 一种用于生成和实现三维（3D）计算机处理芯片堆栈计划的方法，其包括从多个客户端接收系统需求，从系统需求中识别公共处理结构和技术，以及将公共处理结构和技术分配给 三层计算机处理芯片堆栈计划。 该方法还包括从系统需求中识别不常见的处理结构和技术，并将不常见的处理结构和技术分配给3D计算机处理芯片堆栈计划中的主机层。 该方法还包括确定主机层上的不常见结构的布置和布线，将布置信息存储在计划中，并将该计划传送到制造设备。 制造设备生成并集成了包括公共结构和技术的层，以及主机层，包括不常见的结构和技术，以形成3D计算机处理芯片堆栈。