公开(公告)号：US11955446B2

公开(公告)日：2024-04-09

申请号：US17993235

申请日：2022-11-23

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Yu-Han Hsueh

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L24/08 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/80 ,  H01L2224/03011 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0569 ,  H01L2224/05693 ,  H01L2224/08145 ,  H01L2224/09505 ,  H01L2224/80948

摘要： The present disclosure relates to a method for forming a semiconductor device structure. The method includes forming a first semiconductor die and forming a second semiconductor die. The first semiconductor die includes a first metal layer, a first conductive via over the first metal layer, and a first conductive polymer liner surrounding the first conductive via. The second semiconductor die includes a second metal layer, a second conductive via over the second metal layer, and a second conductive polymer liner surrounding the second conductive via. The method also includes forming a conductive structure electrically connecting the first metal layer and the second metal layer by bonding the second semiconductor die to the first semiconductor die. The conductive structure is formed by the first conductive via, the first conductive polymer liner, the second conductive via, and the second conductive polymer liner.

公开(公告)号：US11948991B2

公开(公告)日：2024-04-02

申请号：US17546537

申请日：2021-12-09

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Chen-Hao Lien ,  Cheng-Yan Ji ,  Chu-Hsiang Hsu

IPC分类号： H01L29/45 ,  H10B12/00

CPC分类号： H01L29/456 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/34

摘要： The present disclosure provides semiconductor structure having an electrical contact. The semiconductor structure includes a semiconductor substrate and a doped polysilicon contact. The doped polysilicon contact is disposed over the semiconductor substrate. The doped polysilicon contact includes a dopant material having a dopant concentration equaling or exceeding about 1015 atom/cm3.

公开(公告)号：US11948982B2

公开(公告)日：2024-04-02

申请号：US17456572

申请日：2021-11-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Wan Yu Kai

IPC分类号： H01L29/40 ,  H01L29/417 ,  H01L29/45

CPC分类号： H01L29/401 ,  H01L29/41766 ,  H01L29/456

摘要： A manufacturing method of a semiconductor device includes forming a contact opening in a wafer. The wafer includes a substrate, a gate structure over the substrate and a dielectric layer over the substrate and surrounding the gate structure, and the contact opening passes through the dielectric layer and exposes the substrate. A recess is formed in the substrate such that the recess is connected to the contact opening. An oxidation process is performed to convert a portion of the substrate exposed in the recess to form a protection layer lining a sidewall and a bottom surface of the recess. The protection layer is etched back to remove a first portion of the protection layer in contact with the bottom surface of the recess of the substrate. A metal alloy structure is formed at the bottom surface of the recess of the substrate.

公开(公告)号：US20240105807A1

公开(公告)日：2024-03-28

申请号：US18369962

申请日：2023-09-19

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L29/45 ,  H01L29/40

CPC分类号： H01L29/45 ,  H01L29/401

摘要： The present application discloses a contact structure, a semiconductor device, and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; an impurity region positioned in the substrate; an intervening conductive layer positioned on the impurity region; a bottom conductive layer positioned on the bottom conductive layer; a conductive capping layer positioned on the bottom conductive layer; a top conductive layer positioned on the conductive capping layer. The intervening conductive layer, the bottom conductive layer, the conductive capping layer, and the top conductive layer configure a contact structure. The bottom conductive layer includes germanium or silicon germanium. The bottom conductive layer includes n-type dopants or p-type dopants.

公开(公告)号：US11942514B2

公开(公告)日：2024-03-26

申请号：US18118821

申请日：2023-03-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tse-Yao Huang

IPC分类号： H01L29/06 ,  H01L25/00 ,  H01L25/07

CPC分类号： H01L29/0692 ,  H01L25/072 ,  H01L25/50

摘要： The present application discloses a semiconductor device including a substrate; a first semiconductor stack having a first threshold voltage and comprising a first insulating stack positioned on the substrate; a second semiconductor stack having a second threshold voltage and comprising a second insulating stack positioned on the substrate; and wherein the first threshold voltage is different the second threshold voltage; a thickness of the first insulating stack is different from a thickness of the second insulating stack.

公开(公告)号：US11942331B2

公开(公告)日：2024-03-26

申请号：US17550321

申请日：2021-12-14

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ching-Cheng Chuang

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/31116

摘要： A method for preparing a semiconductor device structure is provided. The method includes forming a target layer over a semiconductor substrate; forming an energy-sensitive layer over the target layer; performing a first energy treating process to form a plurality of first treated portions in the energy-sensitive layer; performing a second energy treating process to form a plurality of second treated portions in the energy-sensitive layer; removing the first treated portions and the second treated portions to respectively form a plurality of first openings and a plurality of second openings; transferring the first openings and the second openings into the target layer to respectively form a plurality of third openings and a plurality of fourth openings; and transferring the third openings and the fourth openings into the semiconductor substrate to respectively form a plurality of fifth openings and a plurality of sixth openings.

公开(公告)号：US11935886B2

公开(公告)日：2024-03-19

申请号：US18209090

申请日：2023-06-13

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Fang-Wen Liu

IPC分类号： H01L27/02 ,  H02H9/04

CPC分类号： H01L27/0288 ,  H01L27/0266 ,  H01L27/0292 ,  H01L27/0296 ,  H02H9/045

摘要： An electrostatic discharge (ESD) protection circuit is provided. The protection circuit includes a MOS transistor and a resistor. The MOS transistor is electrically coupled to a core circuit. The resistor is electrically coupling to a gate of the MOS transistor for creating a bias on the gate to directing an ESD current to a ground when an ESD event occurs on the core circuit. A layout of the MOS transistor is spaced apart from a layout of the core circuit by a layout of a dummy structure. The resistor is formed by utilizing a portion of the dummy structure.

公开(公告)号：US20240090204A1

公开(公告)日：2024-03-14

申请号：US18509601

申请日：2023-11-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H10B12/00

CPC分类号： H10B12/485 ,  H10B12/30 ,  H10B12/482 ,  H10B12/488

摘要： The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.

公开(公告)号：US20240090195A1

公开(公告)日：2024-03-14

申请号：US18368678

申请日：2023-09-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUNG-PENG HAO

IPC分类号： H10B12/00

CPC分类号： H10B12/30 ,  H10B12/05 ,  H10B12/482

摘要： A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a first bit-line extending in a first direction and a first word-line extending in a second direction substantially perpendicular to the first direction. The semiconductor device also includes a first channel. The first bit-line and the first word-line are electrically coupled to the first channel. The semiconductor device also includes a first gate line disposed between the first bit-line and the first word-line. The first gate line is electrically coupled to the first channel and configured to close the first channel once the first bit-line and the first word-line are shorted together through the first channel.

公开(公告)号：US20240074147A1

公开(公告)日：2024-02-29

申请号：US18213977

申请日：2023-06-26

申请人： NANYA TECHNOLOGY CORPORATION

发明人： YI-JEN LO ,  CHIANG-LIN SHIH ,  HSIH-YANG CHIU

IPC分类号： H10B12/00 ,  H01L23/528 ,  H01L23/532

CPC分类号： H10B12/315 ,  H01L23/5283 ,  H01L23/53295 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/488

摘要： A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.