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公开(公告)号：US12046620B2
公开(公告)日：2024-07-23
申请号：US17551427
申请日：2021-12-15
发明人： Yu-Han Hsueh
IPC分类号： H01L27/146
CPC分类号： H01L27/14634 , H01L27/1462 , H01L27/14621 , H01L27/14627 , H01L27/14636 , H01L27/14645 , H01L27/14685 , H01L27/1469
摘要： The present application provides an optical semiconductor device with a composite intervening structure. The optical semiconductor device includes a logic die including a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and including a memory cell area and a memory peripheral area, and a first inter-die via positioned in the memory peripheral area and electrically connected to the logic peripheral circuit area; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area and electrically coupled to the logic peripheral circuit area through the first inter-die via, and a second intra-die via positioned in the sensor peripheral area. The intervening structure is disposed on the back surface of the memory die.
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2.发明授权公开(公告)号：US11569189B2
公开(公告)日：2023-01-31
申请号：US17004889
申请日：2020-08-27
发明人： Yu-Han Hsueh
IPC分类号： H01L23/00
摘要： The present disclosure relates to a semiconductor device structure with a conductive polymer liner and a method for preparing the semiconductor device structure. The semiconductor device structure includes a first metal layer disposed over a semiconductor substrate, and a second metal layer disposed over the first metal layer. The semiconductor device structure also includes a conductive structure disposed between the first metal layer and the second metal layer. The conductive structure includes a first conductive via and a first conductive polymer liner surrounding the first conductive via.
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公开(公告)号：US11581216B2
公开(公告)日：2023-02-14
申请号：US17306254
申请日：2021-05-03
发明人： Yu-Han Hsueh
IPC分类号： H01L21/762 , H01L27/108
摘要： The present disclosure provides a semiconductor device structure with a silicon-on-insulator (SOI) region and a method for forming the semiconductor device structure. The semiconductor device structure also includes a well region disposed in a semiconductor substrate, a first shallow trench isolation (STI) structure extending into the well region. The first STI structure comprises a first liner contacting the well region; a second liner covering the first liner and contacting the pad oxide layer and the pad nitride layer; a third liner covering the second liner, wherein the first liner, the second liner and the third liner are made of different materials; and a first trench filling layer disposed over the third liner and separated from the second liner by the third liner.
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公开(公告)号：US10910221B2
公开(公告)日：2021-02-02
申请号：US16456921
申请日：2019-06-28
发明人： Yu-Han Hsueh
IPC分类号： H01L21/033 , H01L21/311 , H01L23/00
摘要： The present application discloses a semiconductor device structure and a method for forming the same. The method includes forming a pillar over a substrate, forming a first ring structure over a sidewall of the pillar, removing the pillar to form a first opening surrounded by the first ring structure, forming a second ring structure in the first opening, forming a third ring structure surrounding the first ring structure after the first opening is formed, and removing the first ring structure to form a gap between the second and third ring structures. A semiconductor device structure includes a dielectric layer over a substrate, a first ring structure over the dielectric layer, and a second ring structure over the dielectric layer and surrounding the first ring structure, wherein the first and the second ring structures have a first common center.
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5.发明授权公开(公告)号：US11646262B2
公开(公告)日：2023-05-09
申请号：US17352681
申请日：2021-06-21
发明人： Yu-Han Hsueh
IPC分类号： H01L23/522 , H01L23/528 , H01L49/02
CPC分类号： H01L23/5223 , H01L23/5283 , H01L28/87 , H01L28/88
摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.
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公开(公告)号：US11621188B2
公开(公告)日：2023-04-04
申请号：US16846936
申请日：2020-04-13
发明人： Yu-Han Hsueh
IPC分类号： H01L21/768 , H01L21/311
摘要： The present application discloses a method for fabricating a semiconductor device with air gaps for reducing capacitive coupling between conductive features. The method includes the following operations: forming a first conductive line including a first protruding portion protruding from one side of the first conductive line, forming a second conductive line including a second protruding portion facing onto the first protruding portion and protruding from one side of the second conductive line, forming a void between the first protruding portion and the second protruding portion, and performing an etch process to expand the void into an air gap.
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公开(公告)号：US20220352011A1
公开(公告)日：2022-11-03
申请号：US17828253
申请日：2022-05-31
发明人： Yu-Han Hsueh
IPC分类号： H01L21/762 , H01L27/108
摘要： The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a pad oxide layer over a semiconductor substrate; forming a pad nitride layer over the pad oxide layer; forming a shallow trench penetrating through the pad nitride layer and the pad oxide layer and extending into the semiconductor substrate; forming a first liner, a second liner and a third liner over sidewalls and a bottom surface of the semiconductor substrate in the shallow trench; filling a remaining portion of the shallow trench with a trench filling layer over the third liner; and planarizing the second liner, the third liner and the trench filling layer to expose the pad nitride layer. The first liner and the remaining portions of the second liner, the third liner and the trench filling layer collectively form a shallow trench isolation (STI) structure in an array area.
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公开(公告)号：US11955446B2
公开(公告)日：2024-04-09
申请号：US17993235
申请日：2022-11-23
发明人： Yu-Han Hsueh
CPC分类号： H01L24/08 , H01L24/03 , H01L24/05 , H01L24/09 , H01L24/80 , H01L2224/03011 , H01L2224/05547 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/0569 , H01L2224/05693 , H01L2224/08145 , H01L2224/09505 , H01L2224/80948
摘要： The present disclosure relates to a method for forming a semiconductor device structure. The method includes forming a first semiconductor die and forming a second semiconductor die. The first semiconductor die includes a first metal layer, a first conductive via over the first metal layer, and a first conductive polymer liner surrounding the first conductive via. The second semiconductor die includes a second metal layer, a second conductive via over the second metal layer, and a second conductive polymer liner surrounding the second conductive via. The method also includes forming a conductive structure electrically connecting the first metal layer and the second metal layer by bonding the second semiconductor die to the first semiconductor die. The conductive structure is formed by the first conductive via, the first conductive polymer liner, the second conductive via, and the second conductive polymer liner.
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公开(公告)号：US11842960B2
公开(公告)日：2023-12-12
申请号：US18122228
申请日：2023-03-16
发明人： Yu-Han Hsueh
IPC分类号： H01L23/522 , H01L23/528 , H01L23/64 , H01L49/02
CPC分类号： H01L23/5223 , H01L23/5283 , H01L28/86 , H01L28/87 , H01L28/88
摘要： The present application discloses a semiconductor device with a horizontally arranged capacitor. The semiconductor device includes a first palm portion positioned above a substrate; a second palm portion positioned above the substrate and opposite to the first palm portion; a first finger portion arranged substantially in parallel with a main surface of the substrate, positioned between the first palm portion and the second palm portion, and connecting to the first palm portion; a second finger portion arranged substantially in parallel with the first finger portion, positioned between the first palm portion and the second palm portion, and connecting to the second palm portion; a capacitor insulation layer positioned between the first finger portion and the second finger portion; a first spacer positioned between the first palm portion and second finger portion; and a second spacer positioned between the second palm portion and the first finger portion.
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公开(公告)号：US11842921B2
公开(公告)日：2023-12-12
申请号：US17828253
申请日：2022-05-31
发明人： Yu-Han Hsueh
IPC分类号： H01L21/762 , H10B12/00
CPC分类号： H01L21/76283 , H01L21/76267 , H10B12/02 , H10B12/30
摘要： The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a pad oxide layer over a semiconductor substrate; forming a pad nitride layer over the pad oxide layer; forming a shallow trench penetrating through the pad nitride layer and the pad oxide layer and extending into the semiconductor substrate; forming a first liner, a second liner and a third liner over sidewalls and a bottom surface of the semiconductor substrate in the shallow trench; filling a remaining portion of the shallow trench with a trench filling layer over the third liner; and planarizing the second liner, the third liner and the trench filling layer to expose the pad nitride layer. The first liner and the remaining portions of the second liner, the third liner and the trench filling layer collectively form a shallow trench isolation (STI) structure in an array area.
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