公开(公告)号：US20220059400A1

公开(公告)日：2022-02-24

申请号：US17520969

申请日：2021-11-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

摘要： The present disclosure provides an integrated circuit structure with dielectric isolation structure for reducing capacitive coupling and crosstalk between conductive features and a method for preparing the same. The integrated circuit structure includes a plurality of conductive structures disposed over a substrate; a plurality of dielectric structures disposed over the conductive structures; an inter-layer dielectric (ILD) layer disposed over sidewalls of the dielectric structures and sidewalls of the conductive structures, wherein the ILD layer, the dielectric structure and the conductive structure form an air spacer therebetween; and a dielectric isolation structure including a liner layer enclosing an air gap in the ILD layer.

公开(公告)号：US20210265362A1

公开(公告)日：2021-08-26

申请号：US17245727

申请日：2021-04-30

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H01L27/108

摘要： The present disclosure relates to a method for forming a semiconductor device with a conductive cap layer over a conductive plug. The method includes forming a first word line and a second word line over a semiconductor substrate, and forming a dielectric layer covering the first word line and the second word line. The method also includes forming a conductive plug between the first word line and the second word line, wherein the conductive plug is surrounded by the dielectric layer. The method further includes removing a portion of the dielectric layer to partially expose a sidewall surface of the conductive plug, and forming a conductive cap layer covering a top surface and the sidewall surface of the conductive plug. In addition, the method includes forming a bit line over the conductive plug, wherein the bit line is electrically connected to the conductive plug through the conductive cap layer.

公开(公告)号：US20230352588A1

公开(公告)日：2023-11-02

申请号：US18220389

申请日：2023-07-11

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L21/02

CPC分类号： H01L29/785 ,  H01L29/6681 ,  H01L29/41791 ,  H01L29/4991 ,  H01L21/02203

摘要： The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.

公开(公告)号：US20230197768A1

公开(公告)日：2023-06-22

申请号：US18108755

申请日：2023-02-13

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H01L21/02

CPC分类号： H01L28/60

摘要： The present disclosure provides a method for preparing a semiconductor device structure. The method includes forming a capacitor contact over a semiconductor substrate, and forming a base layer over the capacitor contact. The method also includes forming a dielectric layer over the base layer, and performing a first doping process to form a first doped region in the dielectric layer. The method further includes etching the dielectric layer such that a sidewall of the dielectric layer is aligned with a sidewall of the first doped region, and removing the first doped region to form a first gap structure in the dielectric layer after the dielectric layer is etched. In addition, the method includes forming a surrounding portion along sidewalls of the dielectric layer and a first interconnect portion in the first gap structure by a deposition process.

公开(公告)号：US20240090204A1

公开(公告)日：2024-03-14

申请号：US18509601

申请日：2023-11-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H10B12/00

CPC分类号： H10B12/485 ,  H10B12/30 ,  H10B12/482 ,  H10B12/488

摘要： The present disclosure relates to a semiconductor device including a semiconductor substrate, word lines, mask layers, spacers, a conductive plug, a conductive cap layer, and a dielectric layer. The word lines are disposed over the semiconductor substrate. The mask layers are disposed over the plurality of word line, respectively. The spacers are disposed over opposite sidewalls of the word lines and opposite sidewalls of the mask layers, respectively. The conductive plug is disposed between the word lines. The conductive cap layer is disposed over the conductive plug. The dielectric layer is disposed over the word lines and the spacers. Each of the spacers includes an inner spacer, an outer spacer, and an air gap. The inner spacer is in contact with the respective word line and the respective mask layer. The air gap is disposed between the inner spacer and the outer spacer.

公开(公告)号：US20220208955A1

公开(公告)日：2022-06-30

申请号：US17137129

申请日：2020-12-29

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H01L49/02

摘要： The present disclosure provides a semiconductor device structure with a bottom capacitor electrode having a crown-shaped structure and an interconnect portion and a method for forming the same. The semiconductor device structure includes a capacitor contact disposed over a semiconductor substrate, and a dielectric layer disposed over the capacitor contact. The semiconductor device structure also includes a patterned mask disposed over the dielectric layer, and a bottom capacitor electrode disposed over and electrically connected to the capacitor contact. The bottom capacitor electrode includes a base layer disposed between the capacitor contact and the dielectric layer, and a surrounding portion disposed over the base layer and along sidewalls of the dielectric layer and the patterned mask. The bottom capacitor electrode also includes a first interconnect portion disposed in the dielectric layer and substantially parallel to the base layer.

公开(公告)号：US20210234033A1

公开(公告)日：2021-07-29

申请号：US16751168

申请日：2020-01-23

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, two conductive features positioned apart from each other over the substrate, and a porous middle layer positioned between the two conductive features and adjacent to the two conductive features. A porosity of the porous middle layer is between about 25% and about 100%.

公开(公告)号：US20240055521A1

公开(公告)日：2024-02-15

申请号：US18383153

申请日：2023-10-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49 ,  H01L21/02

CPC分类号： H01L29/785 ,  H01L29/6681 ,  H01L29/41791 ,  H01L29/4991 ,  H01L21/02203

摘要： The present application discloses semiconductor device, including a gate structure arranged on a substrate; a plurality of word lines arranged apart from the gate structure; two porous spacers arranged on two sides of the gate structure; and a first insulating layer arranged on the substrate laterally surrounding the gate structure and the porous spacers; and a second insulating layer arranged over the first insulating layer, wherein a top surface of the gate structure, top surfaces of the plurality of word lines and a top surface of the second insulating layer are level with each other, and wherein a porosity of the porous spacers is between about 25% and about 100%.

公开(公告)号：US20220059686A1

公开(公告)日：2022-02-24

申请号：US17516688

申请日：2021-11-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/49

摘要： The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate; forming two conductive features apart from each other over the substrate; forming a porous middle layer positioned between the two conductive features and adjacent to the two conductive features; depositing an energy-removable material between the two conductive features and adjacent to the two conductive features; and performing an energy treatment to transform the energy-removable material into a porous middle layer. The porosity of the porous middle layer is between about 25% and about 100%.

公开(公告)号：US20200373308A1

公开(公告)日：2020-11-26

申请号：US16422608

申请日：2019-05-24

申请人： NANYA TECHNOLOGY CORPORATION

发明人： HUNG-CHI TSAI

IPC分类号： H01L27/108

摘要： A semiconductor device includes a semiconductor substrate, a first word line and a second word line disposed over the semiconductor substrate, and a conductive plug disposed between the first word line and the second word line. The semiconductor device also includes a conductive cap layer disposed over the conductive plug, wherein a top surface and a portion of a sidewall surface of the conductive plug are covered by the conductive cap layer. The semiconductor device further includes a bit line disposed over the conductive cap layer, wherein the bit line is electrically connected to the conductive plug.