公开(公告)号：US08324074B2

公开(公告)日：2012-12-04

申请号：US12557934

申请日：2009-09-11

Applicant: Kangguo Cheng ,  Bruce Doris ,  Pranita Kulkarni

Inventor： Kangguo Cheng ,  Bruce Doris ,  Pranita Kulkarni

IPC: H01L21/76 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224

Abstract: The present invention provides a semiconductor structure comprising high-k material portions that are self-aligned with respect to the active areas in the semiconductor substrate and a method of fabricating the same. The high-k material is protected from oxidation during the fabrication of the semiconductor structure and regrowth of the high-k material and shifting of the high-k material work function is prevented.

Abstract translation: 本发明提供了包括相对于半导体衬底中的有源区自对准的高k材料部分的半导体结构及其制造方法。 在制造半导体结构期间，高k材料被保护免受氧化，并且高k材料的再生长并且防止了高k材料功函数的移位。

公开(公告)号：US20120292710A1

公开(公告)日：2012-11-22

申请号：US13108138

申请日：2011-05-16

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC: H01L27/092 ,  H01L21/3205

CPC classification number: H01L21/823842 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2924/13085 ,  H01L2924/13092

Abstract: A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.

Abstract translation: 半导体器件通过首先提供具有FET对前体的双栅极半导体器件结构形成，其包括nFET前体和pFET前体，其中nFET前体和pFET前体中的每一个包括伪栅极结构。 至少一个保护层沉积在FET对前体之间，留下伪栅极结构。 从nFET前体和pFET前体之一去除伪栅极结构，以在其中分别形成nFET栅极孔和pFET栅极孔中的一个。 填充物沉积在形成的nFET栅极孔和pFET栅极之一中。

公开(公告)号：US20120280365A1

公开(公告)日：2012-11-08

申请号：US13552296

申请日：2012-07-18

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

IPC: H01L29/06

CPC classification number: H01L21/308 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

Abstract: A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

Abstract translation: 公开了一种用于半导体器件的结构。 该结构包括第一特征和第二特征。 第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。 第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

公开(公告)号：US08299530B2

公开(公告)日：2012-10-30

申请号：US12717375

申请日：2010-03-04

Applicant: Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

Inventor： Chengwen Pei ,  Roger A. Booth, Jr. ,  Kangguo Cheng ,  Joseph Ervin ,  Ravi M. Todi ,  Geng Wang

IPC: H01L27/12 ,  H01L21/8238

CPC classification number: H01L21/22 ,  H01L21/8238 ,  H01L27/092

Abstract: A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack. The structure further includes a localized workfunction tuning area located within a portion of at least one of the extension regions that is positioned adjacent the channel region as well as within at least a sidewall portion of the at least one gate stack. The localized workfunction tuning area can be formed by ion implantation or annealing.

Abstract translation: 提供了一种半导体结构及其形成方法，其中通过在pFET的选定部分内引入功函数调谐物质来控制栅极感应漏极泄漏，使得pFET的栅极/ SD（源极/漏极）重叠区域为 适应平带，但不影响设备通道区域的功能。 该结构包括具有位于半导体衬底的pFET器件区域内的至少一个图案化栅叠层的半导体衬底。 所述结构还包括位于所述半导体衬底内的所述至少一个图案化栅叠层的覆盖区的扩展区。 沟道区域也存在并且位于至少一个图案化栅叠层下方的半导体衬底内。 该结构进一步包括位于至少一个延伸区域的一部分内的局部功能调谐区域，其位于邻近通道区域以及至少一个栅极叠层的至少一个侧壁部分内。 通过离子注入或退火可形成局部功能调谐区域。

公开(公告)号：US20120267685A1

公开(公告)日：2012-10-25

申请号：US13539700

申请日：2012-07-02

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823842 ,  H01L21/823857

Abstract: In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.

Abstract translation: 在电路结构中，PFET器件具有栅极电介质，其包括高k电介质，具有金属的栅格，p源极/漏极和形成在p源极/漏极上的硅化物层; NFET器件包括栅极电介质，其包括高k电介质，具有金属的盖板，在n源极/漏极上形成的n源极/漏极和硅化物层。 外延SiGe存在于PFET栅极电介质的下面并与PFET栅极电介质直接接触，而外延SiGe不存在于NFET栅极电介质下方。

公开(公告)号：US08278175B2

公开(公告)日：2012-10-02

申请号：US12813311

申请日：2010-06-10

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC: H01L21/335

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785

Abstract: Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.

Abstract translation: 公开了用于制造FET器件结构的方法。 所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。 氧化物元件在制造Fin-FET器件的鳍片上施加压力。 施加的压力在Fin-FET器件的器件沟道中引起压应力。 所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。 所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。 还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有各自具有鳍片的Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

公开(公告)号：US20120235238A1

公开(公告)日：2012-09-20

申请号：US13048977

申请日：2011-03-16

Applicant: Kangguo Cheng ,  Bruce Doris ,  Pranita Kulkarni ,  Ghavam Shahidi

Inventor： Kangguo Cheng ,  Bruce Doris ,  Pranita Kulkarni ,  Ghavam Shahidi

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/786 ,  H01L29/66772 ,  H01L29/78654 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a semiconductor substrate, an insulating layer, a first semiconductor layer, a dielectric layer, a second semiconductor layer, a source and drain junction, a gate, and a spacer. The method includes the steps of forming a semiconductor substrate, forming a shallow trench isolation layer, growing a first epitaxial layer, growing a second epitaxial layer, forming a gate, forming a spacer, performing a reactive ion etching, removing a portion of the first epitaxial layer, filling the void with a dielectric, etching back a portion of the dielectric, growing a silicon layer, implanting a source and drain junction, and forming an extension.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括半导体衬底，绝缘层，第一半导体层，电介质层，第二半导体层，源极和漏极结，栅极和间隔物。 该方法包括以下步骤：形成半导体衬底，形成浅沟槽隔离层，生长第一外延层，生长第二外延层，形成栅极，形成间隔物，执行反应离子蚀刻，去除第一 外延层，用电介质填充空隙，蚀刻电介质的一部分，生长硅层，注入源极和漏极结，以及形成延伸。

公开(公告)号：US20120223386A1

公开(公告)日：2012-09-06

申请号：US13470393

申请日：2012-05-14

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC: H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/2633 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/517 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

Abstract: Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold- modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.

Abstract translation: 公开了非对称FET器件，以及在翅片结构上制造这种非对称器件的方法。 该制造方法包括在散热片上布置高k电介质层，随后是阈值修饰层，以倾斜角度进行离子轰击，该倾斜角度在翅片的侧面之一上除去阈值修饰层。 完成的FET器件将是不对称的，因为阈值修饰层仅存在于翅片一侧的两个器件之一中。 在替代实施例中，引入另外的不对称性，再次使用倾斜离子注入，导致用于翅片每侧上的两个FinFET器件的不同的栅极 - 导体材料。

公开(公告)号：US20120205732A1

公开(公告)日：2012-08-16

申请号：US13454635

申请日：2012-04-24

Applicant: John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

Inventor： John E. Barth, JR. ,  Kangguo Cheng ,  Michael Sperling ,  Geng Wang

IPC: H01L27/108

CPC classification number: H01L21/76895 ,  H01L23/485 ,  H01L27/10867 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes an active transistor laterally adjacent to a trench capacitor formed in a semiconductor substrate, the active transistor comprising a source junction and a drain junction, wherein a barrier layer is disposed along a periphery of the trench capacitor for isolating the trench capacitor; a passive transistor laterally spaced from the active transistor, wherein at least a portion of the trench capacitor is interposed between the active and passive transistors; an interlevel dielectric disposed upon the active and passive transistors; and a first conductive contact extending through the interlevel dielectric to the drain junction of the active transistor and the at least a portion of the trench capacitor between the active and passive transistors, wherein the first conductive contact electrically connects the trench capacitor to the drain junction of the active transistor.

Abstract translation: 集成电路包括与形成在半导体衬底中的沟槽电容器横向相邻的有源晶体管，所述有源晶体管包括源极结和漏极结，其中阻挡层沿着所述沟槽电容器的外围设置以隔离所述沟槽电容器; 与有源晶体管横向隔开的无源晶体管，其中所述沟槽电容器的至少一部分插入在所述有源和无源晶体管之间; 布置在有源和无源晶体管上的层间电介质; 以及第一导电接触件，其延伸穿过所述有源晶体管的所述有源晶体管和所述沟槽电容器的所述至少一部分的所述层间电介质的漏极结到所述有源和无源晶体管之间，其中所述第一导电接触将所述沟槽电容器电连接到所述沟道电容器 有源晶体管。

公开(公告)号：US08242560B2

公开(公告)日：2012-08-14

申请号：US12688347

申请日：2010-01-15

Applicant: Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

Inventor： Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.

Abstract translation: 提供了一种半导体器件，其在一个实施例中包括在电介质表面之上的至少一个半导体鳍结构，所述半导体鳍结构包括第一导电类型的沟道区和第二导电类型的源区和漏区， 漏区存在于半导体鳍结构的相对端。 具有1.0nm至5.0nm厚度的高k栅介质层与半导体鳍结构的沟道直接接触。 至少一个栅极导体层与高k栅极电介质层直接接触。 还提供了一种形成上述装置的方法。