公开(公告)号：US20230255025A1

公开(公告)日：2023-08-10

申请号：US18136192

申请日：2023-04-18

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Mei Lan Guo ,  Yushi Hu ,  Ji Xia ,  Hongbin Zhu

IPC: H10B41/42 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/42 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: In certain aspects, a semiconductor device includes a substrate, a stack structure over the substrate and including interleaved conductive layers and dielectric layers, and a connection structure extending through the stack structure into the substrate. The connection structure includes a conductor layer and a spacer over a sidewall of the conductor layer. The conductor layer of the connection structure is in direct contact with the substrate.

公开(公告)号：US11690220B2

公开(公告)日：2023-06-27

申请号：US17863367

申请日：2022-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Xiaojuan Gao ,  Chi Ren

IPC: H01L21/00 ,  H10B41/42 ,  H01L29/66 ,  H01L29/788 ,  H10B41/35 ,  H10B41/41

CPC classification number: H10B41/42 ,  H01L29/66825 ,  H01L29/788 ,  H10B41/35 ,  H10B41/41

Abstract: A flash includes a substrate. Two gate structures are disposed on the substrate. Each of the gate structures includes a floating gate and a control gate. The control gate is disposed on the floating gate. An erase gate is disposed between the gate structures. Two word lines are respectively disposed at a side of each of the gate structures. A top surface of each of the word lines includes a first concave surface and a sharp angle. The sharp angle is closed to a sidewall of the word line which the sharp angle resided. The sidewall is away from each of the gate structures. The sharp angle connects to the first concave surface.

公开(公告)号：US11690219B2

公开(公告)日：2023-06-27

申请号：US17332971

申请日：2021-05-27

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Mei Lan Guo ,  Yushi Hu ,  Ji Xia ,  Hongbin Zhu

IPC: H01L27/11531 ,  H10B41/42 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/42 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.