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公开(公告)号：US11165131B2
公开(公告)日：2021-11-02
申请号：US16838664
申请日：2020-04-02
发明人： Wei Xin , Martin Rabindra Pais , MD Rashidul Islam
摘要： Implementations for heat structure for thermal mitigation are described. The described heat structures, for instance, provide a multi-layered structure that optimizes heat spreading and dissipation, as well as wireless performance of wireless devices. A heat structure, for instance, is installed internally in a wireless device adjacent various internal components to absorb heat generated by the components, and to dissipate the heat. According to various implementations, a heat structure is implemented as a thermally conductive layer surrounded by layers of electrically conductive material. Electrically conductive vias can be formed that traverse the thermally conductive layer and form an electrical connection between different electrically conductive layers to mitigate current flow in the thermally conductive layer.
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公开(公告)号：US11101815B2
公开(公告)日：2021-08-24
申请号：US16579203
申请日：2019-09-23
申请人： Fanuc Corporation
发明人： Shinichirou Hayashi
IPC分类号： H03M1/48 , G05B19/414 , G05B19/402
摘要： A control system includes an encoder and a control device that controls a target object. The encoder includes a position information generating unit that generates position information made of a predetermined amount of data and including absolute position data of an object to be detected; a configuration information generating unit that generates configuration information representing a ratio of the absolute position data in the amount of data during serial communication; and a transmission unit that transmits, to the control device, the position information and the configuration information as serial data. The control device includes a reception unit that receives the position information and the configuration information transmitted from the encoder; a storage unit that stores the received configuration information; and a notification unit that performs notification of a configuration mismatch when the stored configuration information does not match the next received configuration information.
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公开(公告)号：US11092464B2
公开(公告)日：2021-08-17
申请号：US16246918
申请日：2019-01-14
发明人： Gary L. Hess , Michael A. Wilson
摘要： A system for determining an amplitude of a sinusoidal output waveform from a sensor includes a controller configured to provide a sample signal having a sample frequency that is four times a frequency of a sinusoidal excitation waveform provided to the sensor. The sensor has inductively-coupled primary and secondary windings that produce the sinusoidal output waveform from the secondary winding when the excitation waveform is provided to the primary winding. An analog-to-digital converter measures a first and second voltage of the sensor waveform separated in time by the period of the sample frequency, and the system calculates the amplitude based on the measurements of the first and second voltages.
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公开(公告)号：US20210184690A1
公开(公告)日：2021-06-17
申请号：US17101575
申请日：2020-11-23
发明人： Jae Won CHOI , Sung Hoon BANG
摘要： A resolver signal processing apparatus processes a resolver signal output from a resolver by applying an excitation signal generated by an excitation signal generating unit. In particular, the resolver signal processing apparatus includes: a resolver signal processing unit, in which the resolver signal processing unit includes a resolver signal acquiring unit receiving the resolver signal and extracting pole information of the resolver signal, a resolver phase compensating unit compensating a pole acquisition time of extracting the pole information of the resolver signal acquiring unit, and a resolver-digital converter outputting a digital signal by using the pole information extracted from the resolver signal acquiring unit, and a resolver signal processing method using the same.
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公开(公告)号：US10958258B2
公开(公告)日：2021-03-23
申请号：US16364239
申请日：2019-03-26
摘要： A comparator includes a pair of back-to-back negative-AND (NAND) gates and a delay circuit coupled to the pair of back-to-back NAND gates. The delay circuit is configured to modulate a triggering clock signal by an input voltage to generate a delayed clock signal with a delay that is based on the input voltage. Each of the pair of back-to-back NAND gates is configured to receive the delayed clock signal and generate a comparator output signal based on the delayed clock signal.
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公开(公告)号：US10911061B2
公开(公告)日：2021-02-02
申请号：US15933991
申请日：2018-03-23
申请人： THE BOEING COMPANY
发明人： Douglas C. Cameron , Dwayne C. Merna , Manu Sharma
摘要： Demodulation circuitry includes an input terminal configured to be coupled to an analog-to-digital converter (ADC) and configured to receive a plurality of ADC outputs. The plurality of ADC outputs are generated based on resolver outputs. The demodulation circuitry also includes a rectifier configured to rectify the plurality of ADC outputs. Rectifying the plurality of ADC outputs preserves a phase of the plurality of ADC outputs. The demodulation circuitry includes amplitude determination circuitry configured to determine, based on the rectified plurality of ADC outputs, demodulated amplitude values corresponding to the resolver outputs. The demodulation circuitry further includes angle computation circuitry configured to generate position outputs based on the demodulated amplitude values.
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公开(公告)号：US10855303B1
公开(公告)日：2020-12-01
申请号：US16820192
申请日：2020-03-16
发明人： Jacques Jean Bertin
摘要： Various embodiments provide a filter for propagation delay compensation and interpolation in encoder digital signal processing. The filter can include a first low pass filter configured to reduce noise of a digital input comprising a measured angular position; a first differentiator configured to receive a filtered digital input and to calculate a speed from a difference in time of the measured angular position and a previous angular position; a second low pass filter configured to reduce noise from the speed; a second differentiator configured to receive a filtered speed and to calculate acceleration using a difference in time of the filtered speed and a previous speed; a third low pass filter configured to reduce noise of the acceleration; and a delay compensator configured to receive the filtered digit input, the filtered speed, and a filtered acceleration, and to calculate a propagation delay compensated digital output.
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公开(公告)号：US10651869B1
公开(公告)日：2020-05-12
申请号：US16364891
申请日：2019-03-26
发明人： Davide Ponton , Michael Kalcher , Alan Paussa , Edwin Thaller , Franz Kuttner , Daniel Gruber
摘要： A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.
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公开(公告)号：US20200099387A1
公开(公告)日：2020-03-26
申请号：US16579203
申请日：2019-09-23
申请人： Fanuc Corporation
发明人： Shinichirou Hayashi
IPC分类号： H03M1/48 , G05B19/402 , G05B19/414
摘要： A control system includes an encoder and a control device that controls a target object. The encoder includes a position information generating unit that generates position information made of a predetermined amount of data and including absolute position data of an object to be detected; a configuration information generating unit that generates configuration information representing a ratio of the absolute position data in the amount of data during serial communication; and a transmission unit that transmits, to the control device, the position information and the configuration information as serial data. The control device includes a reception unit that receives the position information and the configuration information transmitted from the encoder; a storage unit that stores the received configuration information; and a notification unit that performs notification of a configuration mismatch when the stored configuration information does not match the next received configuration information.
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公开(公告)号：US10530383B2
公开(公告)日：2020-01-07
申请号：US16031872
申请日：2018-07-10
发明人： Kazuaki Kurooka , Yoshihiro Funato
摘要： In a semiconductor device, a sine wave signal is input to a first input part and a cosine wave signal is input to a second input part. A multiplexer alternately selects one of the sine wave signal and the cosine wave signal. An analog to digital converter converts the output signal of the multiplexer into a digital value. A switching circuit is coupled between at least one of the first and second input parts and the multiplexer. The switching circuit is configured to be able to invert the input sine wave signal or the input cosine wave signal, in order to reduce the angle detection error due to the non-linearity error of the A/D converter.
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