公开(公告)号：US20040115924A1

公开(公告)日：2004-06-17

申请号：US10657871

申请日：2003-09-09

发明人： Min Yong Lee ,  Yong Seok Eun

IPC分类号： H01L021/425 ,  H01L021/44 ,  H01L021/4763

CPC分类号： H01L27/10888 ,  H01L21/823418 ,  H01L21/823475

摘要： Disclosed is a method of manufacturing semiconductor devices, which can improve electrical characteristics of semiconductor devices. The method of manufacturing comprises the following steps of: forming a plurality of gates on a semiconductor substrate; forming an insulation layer on an entire surface of the semiconductor substrate to coat the plurality of gates; selectively removing the insulation layer by using a first mask pattern to form a contact hole, which exposes a source/drain junction and a conductive layer in a portion of the gates in the semiconductor substrate; removing the first mask pattern and forming a second mask pattern on the selectively removed insulation layer, the second mask pattern exposing the pnull source/drain junction in the semiconductor substrate; implanting ion into the pnull source/drain junction in the semiconductor substrate by using the second mask pattern as a mask; removing the second mask pattern and rapid thermal annealing the entire substrate in a activation temperature range of dopant which is implanted in the ion implantation step; and burying the contact hole with conductive material to form a bit line contact plug. The invention can effectively reduce bit line contact resistance but raise resistance uniformity without variation in related techniques such as etching and contact material for forming contacts.

摘要翻译： 公开了可以改善半导体器件的电气特性的半导体器件的制造方法。 制造方法包括以下步骤：在半导体衬底上形成多个栅极; 在所述半导体衬底的整个表面上形成绝缘层以涂覆所述多个栅极; 通过使用第一掩模图案来形成接触孔来选择性地去除绝缘层，所述接触孔在半导体衬底中的栅极的一部分中暴露出源极/漏极结和导电层; 去除所述第一掩模图案并在所述选择性去除的绝缘层上形成第二掩模图案，所述第二掩模图案暴露所述半导体衬底中的所述p +源极/漏极结; 通过使用第二掩模图案作为掩模将离子注入半导体衬底中的p +源极/漏极结; 在离子注入步骤中注入的掺杂剂的活化温度范围内去除第二掩模图案并对整个基板进行快速热退火; 并用导电材料掩埋接触孔以形成位线接触塞。 本发明可以有效地降低位线接触电阻，但是提高电阻均匀性，而不会在诸如用于形成触点的蚀刻和接触材料等相关技术中发生变化。

公开(公告)号：US20040115892A1

公开(公告)日：2004-06-17

申请号：US10719252

申请日：2003-11-21

发明人： Lance S. Robertson

IPC分类号： H01L021/336 ,  H01L021/04 ,  H01L021/425

CPC分类号： H01L21/02592 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/2022 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/6659

摘要： A method of forming a semiconductor device includes forming at least one amorphous region within an at least partially formed semiconductor device. The method also includes implanting a halogen species in the amorphous region of the at least partially formed semiconductor device. The method further includes doping at least a portion of the at least one amorphous region to form at least one junction within the at least partially formed semiconductor device. The method also includes performing solid phase epitaxial re-growth to activate the doped portion of the at least one amorphous region of the at least partially formed semiconductor device.

公开(公告)号：US20040106236A1

公开(公告)日：2004-06-03

申请号：US10712455

申请日：2003-11-12

发明人： Binghua Hu ,  Howard S. Lee ,  Henry L. Edwards ,  John Lin ,  Vladimir N. Bolkhovsky

IPC分类号： H01L021/332 ,  H01L021/425 ,  H01L021/336

CPC分类号： H01L21/266 ,  H01L21/2652 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

摘要： A double diffused region (65), (75), (85) is formed in an epitaxial layer (20). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer (120) is formed on the epitaxial layer (20) and gate structures (130), (135) are formed over the dielectric layer (120).

摘要翻译： 在外延层（20）中形成双扩散区域（65），（75），（85）。 通过在硬烘烤过程之前首先将诸如硼的光注入物质在光致抗蚀剂层中的开口注入，形成双扩散区域。 在硬烘烤过程之后，可以将诸如砷的重植入物种植入外延层中。 在后续处理（如LOCOS形成）中形成双扩散区。 在外延层（20）上形成电介质层（120），并且在电介质层（120）之上形成栅极结构（130），（135）。

公开(公告)号：US20040087118A1

公开(公告)日：2004-05-06

申请号：US10608154

申请日：2003-06-30

申请人： Renesas Technology Corp. ,  Ion Engineering Research Institute, Corporation ,  Natsuro Tsubouchi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Kazunobu Ohta ,  Yasuo Inoue ,  Masanobu Kohara ,  Takashi Eura ,  Natsuro Tsubouchi

IPC分类号： H01L021/425 ,  H01L021/26 ,  H01L021/42 ,  H01L021/22 ,  H01L021/38 ,  H01L021/324 ,  H01L021/477

CPC分类号： H01L21/268 ,  H01L21/2652 ,  H01L21/28518 ,  H01L29/6659

摘要： Activation of impurities is achieved without involving creation of a crystal defect or deformation by using phonon absorption. A laser beam (42) having a wavelength in a range of 16 to 17 nullm is irradiated onto silicon, to cause phonon absorption. Before an energy supplied from the laser beam (42) diffuses around a portion which is irradiated with the laser beam (42), solid phase epitaxy in the portion finishes. Accordingly, crystallization occurs only in the portion which is irradiated with the laser beam (42), and does not occur in a portion which is not irradiated with the laser beam (42). Hence, heat is not excessively absorbed. Also, local phase change such as melting and solidification is not caused.

摘要翻译： 实现杂质的活化而不涉及通过使用声子吸收产生晶体缺陷或变形。 将具有16至17μm波长范围的激光束（42）照射到硅上以引起声子吸收。 在从激光束（42）供给的能量在激光束（42）的一部分附近扩散之前，该部分的固相外延结束。 因此，仅在被激光束（42）照射的部分中发生结晶，不会发生在不被激光束（42）照射的部分。 因此，热量不会被过度吸收。 此外，不会引起局部相变，如熔化和凝固。

公开(公告)号：US20040038504A1

公开(公告)日：2004-02-26

申请号：US10619193

申请日：2003-07-14

发明人： Hiroyuki Ito

IPC分类号： H01L021/425 ,  H01L021/30 ,  H01L021/46 ,  H01L021/265

CPC分类号： H01L21/76254 ,  H01J27/18 ,  H01J37/08 ,  H01J2237/31701 ,  H01L21/26506 ,  Y10S438/961

摘要： Disclosed are an ion implantation method capable of dramatically increasing an implantation rate of hydrogen ions into a semiconductor substrate and a method for manufacturing an SOI wafer, in which manufacturing efficiency of the SOI wafer is sufficiently high. When the hydrogen ions are implanted to a predetermined depth of the semiconductor substrate, hydrogen gas is introduced into a chamber where an inner pressure is reduced and a predetermined magnetic field is formed, plasma is generated by introducing a microwave into the magnetic field, hydrogen ion beams containing hydrogen molecule ions is extracted from the plasma, and the hydrogen molecule ions are irradiated and implanted onto the semiconductor substrate. Thus, a throughput in the hydrogen ion implantation is improved, thus making it possible to enhance the manufacturing efficiency of the SOI wafer.

摘要翻译： 公开了能够显着提高氢离子注入半导体衬底的离子注入方法以及SOI晶片的制造效率足够高的SOI晶片的制造方法。 当将氢离子注入到半导体衬底的预定深度时，将氢气引入到内部压力降低并形成预定磁场的室中，通过将微波引入磁场而产生等离子体，氢离子 从等离子体中提取含有氢分子离子的光束，并将氢分子离子照射并注入到半导体基板上。 因此，提高了氢离子注入中的生产量，从而可以提高SOI晶片的制造效率。

公开(公告)号：US20030235972A1

公开(公告)日：2003-12-25

申请号：US10460292

申请日：2003-06-11

申请人： Dainippon Screen Mfg. Co., Ltd.

发明人： Akihiro Hosokawa

IPC分类号： A61N005/00 ,  G21G005/00 ,  H01L021/425 ,  H01L021/31 ,  H01L021/469

CPC分类号： H01L21/67115 ,  G21K5/04 ,  H01L21/2686

摘要： Each of a plurality of flash lamps forming a light source is a bar lamp having an elongated cylindrical shape. The ratio of the distance between the flash lamps and a semiconductor wafer to the distance between the flash lamps and a reflector is set to not more than 1.8 or at least 2.2. Consequently, illuminance is weakened on portions of the main surface of the semiconductor wafer located immediately under the flash lamps along the vertical direction and strengthened in portions located immediately under the clearances between adjacent ones of the flash lamps along the vertical direction, thereby reducing illuminance irregularity on the overall main surface of the semiconductor wafer and improving in-plane uniformity of temperature distribution on the semiconductor wafer. Thus, a thermal processing apparatus capable of improving in-plane uniformity of temperature distribution on a substrate is provided.

摘要翻译： 形成光源的多个闪光灯中的每一个都是具有细长圆柱形状的条形灯。 闪光灯与半导体晶片之间的距离与闪光灯与反射器之间的距离的比率设定为不大于1.8或至少2.2。 因此，沿着垂直方向位于闪光灯正下方的半导体晶片的主表面的部分上的照度被削弱，并且在垂直方向上位于相邻闪光灯之间的间隙正下方的部分被加强，由此减小照度不均匀 在半导体晶片的整个主表面上，提高半导体晶片上的温度分布的面内均匀性。 因此，提供能够提高基板上的温度分布的面内均匀性的热处理装置。

公开(公告)号：US20030232284A1

公开(公告)日：2003-12-18

申请号：US10064113

申请日：2002-06-12

发明人： Chien-Hung Liu ,  Shyi-Shuh Pan ,  Shou-Wei Huang ,  Ying-Tso Chen ,  Erh-Kun Lai

IPC分类号： G03F007/16 ,  G03F007/20 ,  G03F007/40 ,  H01L021/20 ,  H01L021/36 ,  H01L021/425 ,  H01L021/311 ,  H01L021/31 ,  H01L021/469

CPC分类号： H01L27/11568 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11573

摘要： A method of forming a system on chip(SOC) comprising read only memory(ROM) and nitride read only memory(NROM) by utilizing nitride read only memory. The method is to form a plurality of field oxide layers on a surface of a substrate in order to define an active area of each device. An ONO dielectric layer is then formed on the surface of the substrate, thereafter performing a photolithography and ion implantation process to form a plurality of N-type bit lines and P-type pocket doping areas in the substrate inside the memory area. After that, an etching process is performed in order to remove regions of the ONO dielectric layer in the periphery area and regions of the ONO dielectric layer in the memory area, optionally. After that, a thermal oxidation process is utilized in order to form a buried drain oxide layer atop each bit line and a gate oxide layer on the surface of the active area in the periphery area, respectively. Then, a polysilicon layer is deposited on the surface of the substrate and a photolithography and etching process are utilized in order to simultaneously form a word line in the memory area and the gates of the periphery transistor in the periphery area. Finally, a ROM code process is performed to adjust the threshold voltage of the high threshold voltage(high Vth) device in the read only memory area.

摘要翻译： 通过利用氮化物只读存储器形成包括只读存储器（ROM）和氮化物只读存储器（NROM）的片上系统（SOC）的方法。 该方法是在衬底的表面上形成多个场氧化物层，以便限定每个器件的有效面积。 然后在衬底的表面上形成ONO电介质层，然后进行光刻和离子注入工艺，以在存储区域内的衬底中形成多个N型位线和P型口袋掺杂区域。 之后，进行蚀刻处理，以便可选地除去存储区域中的ONO介电层的周边区域和区域中的ONO电介质层的区域。 之后，利用热氧化工艺，以分别在周边区域的有源区域的表面上的每个位线和栅极氧化物层的顶部形成掩埋的漏极氧化层。 然后，在衬底的表面上沉积多晶硅层，并利用光刻和蚀刻工艺，以便在周边区域的存储区域和外围晶体管的栅极中同时形成字线。 最后，执行ROM代码处理以在只读存储器区域中调整高阈值电压（高Vth）器件的阈值电压。

公开(公告)号：US20030216014A1

公开(公告)日：2003-11-20

申请号：US10394665

申请日：2003-03-24

申请人： APPLIED MATERIALS, INC.

发明人： Richard David Goldberg

IPC分类号： H01L021/04 ,  C23C014/00 ,  H01L021/425

CPC分类号： H01J37/08 ,  H01J2237/31701

摘要： Monotomic boron ions for ion implantation are supplied from decaborane vapour. The vapour is fed to a plasma chamber and a plasma produced in the chamber with sufficient energy density to disassociate the decaborane molecules to produce monatomic boron ions in the plasma.

摘要翻译： 用于离子注入的单根硼离子由十硼烷蒸气提供。 将蒸汽送入等离子体室和在室中产生的等离子体具有足够的能量密度，以分离出十硼烷分子以在等离子体中产生单原子硼离子。

公开(公告)号：US20030207542A1

公开(公告)日：2003-11-06

申请号：US10139672

申请日：2002-05-06

发明人： P.R. Chidambaram ,  Amitava Chatterjee ,  Srinivasan Chakravarthi

IPC分类号： H01L021/336 ,  H01L021/425

CPC分类号： H01L29/6656 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586

摘要： The present invention is directed to a method of forming a PMOS transistor within a semiconductor substrate, and comprises forming a gate over an n-type portion of the semiconductor substrate, thereby defining a source region and a drain region in the semiconductor substrate with a channel region therebetween. The source and drain region of the semiconductor substrate are then subjected to an angled amorphization implant, wherein the angled amorphization implant amorphizes the semiconductor substrate thereat and in portions of the channel region near a lateral edge of the gate, thereby defining an amorphized source extension region and drain extension region, respectively. The method continue with an implantation of the source region and the drain region with a lightly doped p-type source/drain implant, followed by an anneal to repair damage in the semiconductor substrate due to the pre-amorphizing implant and the lightly doped source/drain implantation. The amorphized source and drain extension regions advantageously reduce a lateral diffusion thereof during the anneal.

摘要翻译： 本发明涉及一种在半导体衬底内形成PMOS晶体管的方法，包括在半导体衬底的n型部分上形成栅极，由此在沟道中限定半导体衬底中的源极区和漏极区 区域。 然后对半导体衬底的源极和漏极区域进行成角度的非晶化注入，其中成角度的非晶化植入物使半导体衬底在其上方和在栅极的侧边缘附近的沟道区域的部分中非晶化，从而限定非晶化源极延伸区域 和漏极延伸区域。 该方法继续用轻掺杂的p型源极/漏极注入来注入源极区域和漏极区域，随后进行退火以修复半导体衬底中的损伤，这是由于预非晶化注入和轻掺杂源极/ 漏极植入。 非晶化源极和漏极延伸区域有利地在退火期间减小其横向扩散。

公开(公告)号：US20030199154A1

公开(公告)日：2003-10-23

申请号：US10438360

申请日：2003-05-14

发明人： Vishnu K. Agarwal

IPC分类号： H01L021/3205 ,  H01L021/4763 ,  H01L021/425

CPC分类号： H01L21/28061 ,  H01L21/28247 ,  H01L21/76838 ,  H01L27/10873 ,  H01L27/10891 ,  H01L29/4941 ,  H01L2924/0002 ,  H01L2924/00

摘要： In accordance with one embodiment of the present invention, a method of interfacing a poly-metal stack and a semiconductor substrate is provided where an etch stop layer is provided in a polysilicon region of the stack. The present invention also addresses the relative location of the etch stop layer in the polysilicon region and a variety of stack materials and oxidation methods. The etch stop layer may be patterned within the poly or may be a continuous conductive etch stop layer in the poly. The present invention also relates more broadly to a process for forming wordline architecture of a memory cell. In accordance with another embodiment of the present invention, a semiconductor structure is provided comprising a poly-metal stack formed over a semiconductor substrate where the interface between an oxidation barrier placed over the stack and an oxidized portion of the stack lies along the sidewall of the poly. A semiconductor structure is also provided where a conductive layer is present in the poly region of the poly-metal stack. The present invention also relates more broadly to a memory cell array and a computer system including the poly-metal stack of the present invention.

摘要翻译： 根据本发明的一个实施例，提供了一种连接多金属堆叠和半导体衬底的方法，其中在堆叠的多晶硅区域中提供蚀刻停止层。 本发明还解决了多晶硅区域中的蚀刻停止层的相对位置以及各种堆叠材料和氧化方法。 蚀刻停止层可以在聚合物内图案化，或者可以是聚合物中的连续的导电蚀刻停止层。 本发明还更广泛地涉及用于形成存储器单元的字线结构的方法。 根据本发明的另一实施例，提供一种半导体结构，其包括形成在半导体衬底上的多金属叠层，其中放置在堆叠上的氧化屏障与堆叠的氧化部分之间的界面沿着 聚 还提供半导体结构，其中导电层存在于多金属叠层的多个区域中。 本发明还更广泛地涉及包括本发明的多金属叠层的存储单元阵列和计算机系统。