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公开(公告)号：US20210191732A1
公开(公告)日：2021-06-24
申请号：US16721833
申请日：2019-12-19
发明人： Michael L. Schmit , Lakshmi Kumar
摘要： A processing device is provided which comprises memory and a processor. The processor is configured to receive an array of floating point numbers each having a plurality of bits used to represent a probability value. For each floating point number, the processor is configured to replace values in a portion of the bits used to represent the probability value with index values to represent an index corresponding to a location of a corresponding floating point number in the memory. The processor is also configured to process the floating point numbers using SIMD instructions to execute one of an argmax operation and an argmin operation.
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公开(公告)号：US11003818B1
公开(公告)日：2021-05-11
申请号：US16790578
申请日：2020-02-13
申请人： Xilinx, Inc.
IPC分类号： G06F30/00 , G06F30/33 , G06F9/30 , G06F30/3308 , G06F7/499
摘要： A method includes parsing and compiling a software code that includes a constraint bitwise operation with a first operand associated with a first constraint range and a second operand associated with a second constraint range. A first and a second plurality of ranges that spans the first and second constraint range are generated. In some embodiments, each constrained range is converted into a binary format having an upper bit portion and a lower bit portion. The upper bit portion for the each range remains unchanged. A resultant range associated with the constraint bitwise operation is determined based on performing the constraint bitwise operation on the first and the second plurality of ranges.
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公开(公告)号：US10956126B2
公开(公告)日：2021-03-23
申请号：US16415178
申请日：2019-05-17
摘要： Execution of a machine instruction in a central processing unit. A perform floating-point operation instruction and a test bit are obtained. If the test bit has a first value, a specified floating-point operation function is performed, and a condition code is set to a value determined by the specified function. If the test bit has a second value, a check is made to determine if the specified function is valid and installed on the machine. If the specified function is valid and installed on the machine, the condition code is set to one code value, and if the specified function is either not valid or not installed on the machine, the condition code is set to a second code value.
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公开(公告)号：US20210072958A1
公开(公告)日：2021-03-11
申请号：US16975013
申请日：2019-02-22
申请人： Octavo Systems LLC
摘要： The present disclosure describes a mixed signal arithmetic logic unit configured to use a combination of analog processing elements and digital processing elements in a cohesive manner. Depending on the signals and the data received for processing, the analog processing elements and digital processing elements may be used separately, independently or in combination to optimize computational results and the performance of the mixed signal arithmetic logic unit.
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55.发明授权公开(公告)号：US10942706B2
公开(公告)日：2021-03-09
申请号：US15633792
申请日：2017-06-27
申请人： Intel Corporation
发明人： Martin Langhammer , Bogdan Pasca
摘要： The present embodiments relate to integrated circuits with circuitry that implements floating-point trigonometric functions. The circuitry may include an approximation circuit that generates an approximation of the output of the trigonometric functions, a storage circuit that stores predetermined output values of the trigonometric functions, and a selector circuit that selects between different possible output values based on a control signal from a control circuit. In some embodiments, the circuitry may include a mapping circuit and a restoration circuit. The mapping circuit may map an input value from an original quadrant of the trigonometric circle to a predetermined input interval, and the restoration circuit may map the output value selected by the selection circuit back to the original quadrant of the trigonometric circle. If desired, the circuitry may be implemented in specialized processing blocks.
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公开(公告)号：US20210034328A1
公开(公告)日：2021-02-04
申请号：US16525720
申请日：2019-07-30
摘要： A computer-implemented method includes: receiving, using a processor, a decimal floating point number; and using a floating point unit within the processor to convert the decimal floating point number into a binary coded decimal number, wherein the floating point unit starts a conversion loop subsequent to a rounding loop starting, wherein the rounding loop and the conversion loop run in parallel once started.
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公开(公告)号：US20210012192A1
公开(公告)日：2021-01-14
申请号：US16898493
申请日：2020-06-11
申请人： FUJITSU LIMITED
发明人： MAKIKO ITO
摘要： An arithmetic processing apparatus includes: a memory that stores, when a training of a given machine learning model is repeatedly performed in a plurality of iterations, an error of a decimal point position of each of a plurality of fixed-point number data obtained one in each of the plurality of iterations, the error being obtained baaed on statistical information related to a distribution of leftmost set bit positions for positive number and leftmost unset bit positions for negative number or a distribution of rightmost set bit positions of the plurality of fixed-point number data; and a processor coupled to the memory, the processor being configured to: determine, based on a tendency of the error in each of the plurality of iterations, an offset amount for correcting a decimal point position of fixed-point number data used in the training.
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公开(公告)号：US10891109B2
公开(公告)日：2021-01-12
申请号：US16158380
申请日：2018-10-12
申请人： FUJITSU LIMITED
发明人： Katsuhiro Yoda , Makiko Ito
摘要： An arithmetic processor includes a plurality of arithmetic circuits that individually execute an arithmetic operation for fixed point data; and at least one of first and second statistical information is acquired regarding a plurality of fixed point data that are results of arithmetic operation executed by the plurality of arithmetic circuits. The first statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from a least-significant-bit position to a highest-order bit position for each of the digits corresponding to the bit positions, and the second statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from the position of the sign bit to a lowest-order-bit position for each of the digits corresponding to the bit positions.
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公开(公告)号：US20200293281A1
公开(公告)日：2020-09-17
申请号：US16550565
申请日：2019-08-26
申请人： Arm Limited
发明人： Javier Diaz BRUGUERA
摘要： A data processing apparatus is provided to convert a plurality of signed digits to an output value. Receiver circuitry receives, at each of a plurality of iterations, one of the plurality of signed digits, each of the signed digits comprising a number of bits dependent on a radix. The signed digits being used to form an unrounded output value followed by zero or more extra bits. Adjustment circuitry adjusts a least-significant digit of the unrounded output value to produce an incremented unrounded output value after the plurality of iterations. Rounding circuitry selects from among the unrounded output value and the incremented unrounded output value to produce the output value. The adjustment circuitry is adapted, when a value of a position of a least-significant bit of the unrounded output value is greater than or equal to the radix divided by two, to adjust a subset of the digits of the unrounded output value.
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公开(公告)号：US10776108B2
公开(公告)日：2020-09-15
申请号：US16163790
申请日：2018-10-18
发明人： Jing Chen , Xiaoyang Li , Juanli Song , Zhenhua Huang , Weilin Wang , Jiin Lai
摘要： A microprocessor provides at least two storage areas and uses a datapath for Booth multiplication. According to a first and second field of a microinstruction, the datapath gets multiplicand number supply data from the first storage area and multiplier number supply data from the second storage area. The datapath operates according to a word length indicated in a third field of the microinstruction. The datapath gets multi-bit acquisitions for Booth multiplication from the multiplier number supply data. The datapath divides the multiplicand number supply data into multiplicand numbers according to the word length, and performs Booth multiplication on the multiplicand numbers based on the multi-bit acquisitions to get partial products. According to the word length, the datapath selects a part of the partial products to be shifted and added for generation of a plurality of products.
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