公开(公告)号：US06647502B1

公开(公告)日：2003-11-11

申请号：US09352384

申请日：1999-07-13

Applicant: Mutsuhiro Ohmori

Inventor： Mutsuhiro Ohmori

IPC: G06F132

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A power supply controlling circuit by which further reduction of power consumption in a circuit can be achieved includes a clock controller. The clock controller detects a processing state of a module based on an amount of data stored in a FIFO memory. For example, when the load to the module is not very high, the clock controller continuously lowers the frequency of a system clock signal to be supplied to the module and continuously lowers the power supply voltage to the module.

Abstract translation: 可以实现电路中的功耗的进一步降低的电源控制电路包括时钟控制器。 时钟控制器基于存储在FIFO存储器中的数据量来检测模块的处理状态。 例如，当模块的负载不是很高时，时钟控制器持续降低要提供给模块的系统时钟信号的频率，并持续降低模块的电源电压。

公开(公告)号：US06636976B1

公开(公告)日：2003-10-21

申请号：US09608748

申请日：2000-06-30

Applicant: Edward T. Grochowski ,  David Sager ,  Vivek Tiwari ,  Ian Young ,  David J. Ayers

Inventor： Edward T. Grochowski ,  David Sager ,  Vivek Tiwari ,  Ian Young ,  David J. Ayers

IPC: G06F132

CPC classification number: G06F1/3237 ,  G06F1/28 ,  G06F1/3203 ,  Y02D10/128

Abstract: The present invention provides a mechanism for adjusting the activity of an integrated digital circuit such as a processor to reduce voltage changes attributable to current changes triggered by clock gating. The processor includes one or more functional units and a current control circuit that monitors activity states of the processor's functional units to estimate the current consumed over n clock cycles. The current control circuit estimates the current change for a given clock cycle from the n activity states and compares the estimated current change with first and second thresholds. The processors activity is decreased if the estimated current change is greater than the first threshold, and the processor activity is decreased if the estimated current change is less than the second threshold.

Abstract translation: 本发明提供一种用于调整诸如处理器的集成数字电路的活动性的机构，以减少归因于由时钟门控触发的电流变化的电压变化。 处理器包括一个或多个功能单元和电流控制电路，其监视处理器的功能单元的活动状态以估计在n个时钟周期内消耗的电流。 电流控制电路从n个活动状态估计给定时钟周期的电流变化，并将估计的电流变化与第一和第二阈值进行比较。 如果估计的电流变化大于第一阈值，则处理器活动减小，并且如果估计的电流变化小于第二阈值，则处理器活动性降低。

公开(公告)号：US06622253B2

公开(公告)日：2003-09-16

申请号：US09920692

申请日：2001-08-02

Applicant: Kinney C. Bacon

Inventor： Kinney C. Bacon

IPC: G06F132

CPC classification number: G06F9/3869 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/329 ,  G06F9/3851 ,  Y02D10/126 ,  Y02D10/24

Abstract: The preferred embodiment of the present invention varies the speed of processor execution, including associating a clock rate with each thread in a plurality of threads and executing each thread in the plurality of threads on the processor at the clock rate associated with the thread.

Abstract translation: 本发明的优选实施例改变处理器执行的速度，包括将时钟速率与多个线程中的每个线程相关联，并且以与线程相关联的时钟速率执行处理器上的多个线程中的每个线程。

公开(公告)号：US06601180B1

公开(公告)日：2003-07-29

申请号：US09549873

申请日：2000-04-14

Applicant: Vladimir Paredes ,  Lomberto Jimenez ,  Vu Thanh

Inventor： Vladimir Paredes ,  Lomberto Jimenez ,  Vu Thanh

IPC: G06F132

CPC classification number: G06F1/3209 ,  G06F1/3203 ,  G06F1/3281 ,  Y02D10/158

Abstract: A method and system for providing link detection to a PC Card for power management. Specifically, one embodiment of the present invention includes a method for reducing power consumption by a peripheral component coupled to a host computer. For instance, the method includes the step of detecting whether a peripheral component is coupled to an active communication link. The method also includes the step of determining whether a circuit of the peripheral component is within a first power consuming mode (e.g., high power consuming mode). Provided the peripheral component is not coupled to the active communication link and the circuit of the peripheral component is within the first power consuming mode, the method includes the step of causing the circuit to enter a second power consuming mode (e.g., a sleep mode). Furthermore, provided the peripheral component is coupled to the active communication link and the circuit of the peripheral component is not within the first power consuming mode, the method includes the step of causing the circuit to enter the first power consuming mode (e.g., high power consuming mode).

Abstract translation: 一种用于向PC卡提供链路检测以进行电源管理的方法和系统。 具体地，本发明的一个实施例包括一种用于降低耦合到主计算机的外围组件的功耗的方法。 例如，该方法包括检测外围组件是否耦合到主动通信链路的步骤。 该方法还包括确定外围组件的电路是否处于第一功耗模式（例如，高功耗模式）内的步骤。 如果外围组件没有耦合到有源通信链路，并且外围组件的电路处于第一功耗模式之内，则该方法包括使电路进入第二功耗模式（例如睡眠模式）的步骤， 。 此外，如果外围组件耦合到主动通信链路，并且外围组件的电路不在第一功耗模式中，则该方法包括使电路进入第一功耗模式（例如，高功率）的步骤 消费模式）。

公开(公告)号：US06574738B2

公开(公告)日：2003-06-03

申请号：US10194617

申请日：2002-07-11

Applicant: Satchit Jain ,  Sun-Soo Cho

Inventor： Satchit Jain ,  Sun-Soo Cho

IPC: G06F132

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: An integrated circuit contains a central processing unit (“CPU”), a graphic control hub (“GCH”), a memory control hub (“MCH”), and a phase lock loop (“PLL”). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transactions. The PLL is configured to allow the CPU to operate at more than one power consumption states.

公开(公告)号：US06542996B1

公开(公告)日：2003-04-01

申请号：US09459771

申请日：1999-12-13

Applicant: Nai-Shung Chang ,  Jang-Lih Hsieh

Inventor： Nai-Shung Chang ,  Jang-Lih Hsieh

IPC: G06F132

CPC classification number: G06F1/3203

Abstract: A method and the associated devices for implementing a suspend-to-RAM (STR) mode of operation in a computer system utilizing the self-refreshing capability of synchrotron DRAM. To switch into the STR mode of operation, system memory data in a first control chip (the north bridge) is first transferred to a memory unit under the direction of a second control chip (the south bridge). The voltage level at the clock-enable pin of the system memory is pulled down under the direction of the south bridge or the north bridge. Power to the north bridge is cut upon receiving a signal from a basic input/output system.

Abstract translation: 一种用于在利用同步加速器DRAM的自刷新能力的计算机系统中实现挂起到RAM（STR）操作模式的方法和相关联的装置。 为了切换到STR操作模式，第一控制芯片（北桥）中的系统存储器数据首先在第二控制芯片（南桥）的方向传送到存储器单元。 系统存储器的时钟使能引脚的电压在南桥或北桥的方向被拉下。 从基本的输入/输出系统接收到信号时，北桥的电源被切断。

公开(公告)号：US06523127B1

公开(公告)日：2003-02-18

申请号：US09334800

申请日：1999-06-16

Applicant: Shigeru Takasu

Inventor： Shigeru Takasu

IPC: G06F132

CPC classification number: G06F1/3265 ,  G06F1/3203 ,  Y02D10/153

Abstract: A display apparatus connected to a personal computer for carrying out character display or graphic display in accordance with information from the personal computer, which is installed with a power saving button for instructing a shift to a power saving mode for reducing power consumption and a micro controller for determining input of the power saving button and controlling a power supply, a deflection circuit and an image circuit to shift to the power saving mode.

Abstract translation: 一种连接到个人计算机的显示装置，用于根据来自个人计算机的信息执行字符显示或图形显示，该个人计算机安装有用于指示转换到省电模式以降低功耗的省电按钮和微控制器 用于确定省电按钮的输入和控制电源，偏转电路和图像电路以转换到省电模式。

公开(公告)号：US06510525B1

公开(公告)日：2003-01-21

申请号：US09300075

申请日：1999-04-26

Applicant: Narasimha Nookala ,  Prahlad Venkatapuram

Inventor： Narasimha Nookala ,  Prahlad Venkatapuram

IPC: G06F132

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/3265 ,  G06F1/3287 ,  G06F3/1438 ,  G09G2330/021 ,  Y02D10/128 ,  Y02D10/153 ,  Y02D10/171

Abstract: An apparatus to power up an integrated device from a low power state wherein the clock circuit for generating the internal clocks has been disabled is provided. A small set of programmable registers is reserved inside the CPU interface unit (CIF) of an integrated device (e.g., a display/graphics controller) which can be accessed by the CPU even during a low power state mode (e.g., software controlled sleep mode D3 in the preferred embodiment). The programmable registers store programmed bits that are used in indicating to the Power Management Unit (PMU) the desired power state and whether the clock circuits are to be enabled or disabled. The programmable registers also store multiplication and division factors to be used by the clock circuits in determining their clock rate. Using this information, the integrated device can go through a predetermined power sequence to transition from the low power state to the normal state which includes powering up the clock circuits (e.g., PLLs and oscillator).

Abstract translation: 提供了一种用于从低功率状态加电集成器件的装置，其中用于产生内部时钟的时钟电路已经被禁止。 即使在低功耗状态模式（例如，软件控制睡眠模式）下也可由CPU访问的集成设备（例如，显示/图形控制器）的CPU接口单元（CIF）中保留一小组可编程寄存器 D3）。 可编程寄存器将用于指示电源管理单元（PMU）的编程位存储在所需的电源状态以及是否使能或禁止时钟电路。 可编程寄存器还存储时钟电路在确定其时钟速率时使用的乘法和除法系数。 使用该信息，集成设备可以经历预定的功率序列，以从低功率状态转换到包括上电时钟电路（例如PLL和振荡器）的正常状态。

公开(公告)号：US06487668B2

公开(公告)日：2002-11-26

申请号：US09782680

申请日：2001-02-12

Applicant: C. Douglass Thomas ,  Alan E. Thomas

Inventor： C. Douglass Thomas ,  Alan E. Thomas

IPC: G06F132

CPC classification number: G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  Y02D10/126 ,  Y02D10/16

Abstract: Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device.

Abstract translation: 公开了用于为计算设备提供热和电源管理的改进方法。 这些方法有助于智能控制处理器的时钟频率和/或风扇的速度，以便为计算设备提供热和/或功率管理。

公开(公告)号：US06470457B1

公开(公告)日：2002-10-22

申请号：US09211366

申请日：1998-12-14

Applicant: James A. Brewer ,  Sanjay Gupta

Inventor： James A. Brewer ,  Sanjay Gupta

IPC: G06F132

CPC classification number: G06F1/3209 ,  G06F1/26 ,  G06F1/32

Abstract: A network computer including, a chassis, a power supply affixed to an interior surface of the chassis, a motherboard powered by the power supply, the motherboard including a clock generator, a boot code storage device, a processor, and a system memory, and a network interface suitable for interfacing the network computer to a server computer via a network. The network computer lacks a disk drive, but includes local permanent storage such as a compact flash card. Preferably, the network computer includes one or more peripheral devices connected to a peripheral bus of the computer. In the preferred embodiment, the network interface provides is an Ethernet compliant connection with an RJ45 connector. In one embodiment, the power supply powers the motherboard via a single power plane. In one embodiment, the network computer includes disk drive facilities for receiving a disk drive. The invention further contemplates a method of testing a network computer including connecting a disk based storage device to a network computer that lacks a disk based storage device but includes local permanent storage, such as a compact flash card. A disk based operating system is then loaded on the network computer via the disk based storage device. A test suite supported by the disk based operating system is then loaded and executed on the network computer to verify its functionality. In one embodiment, the method further includes similarly installing the disk based storage device in each of a plurality of network computers, whereby a single disk based storage device is used to verify each a plurality of network computers.

Abstract translation: 一种网络计算机，包括机箱，固定在机箱内表面的电源，由电源供电的母板，主板包括时钟发生器，引导代码存储装置，处理器和系统存储器，以及 适于通过网络将网络计算机连接到服务器计算机的网络接口。 网络计算机缺少磁盘驱动器，但包括本地永久存储，如小型闪存卡。 优选地，网络计算机包括连接到计算机的外围总线的一个或多个外围设备。 在优选实施例中，网络接口提供与RJ45连接器的以太网兼容连接。 在一个实施例中，电源通过单个电源平面为主板供电。 在一个实施例中，网络计算机包括用于接收磁盘驱动器的磁盘驱动器设备。 本发明进一步考虑了一种测试网络计算机的方法，包括将基于盘的存储设备连接到缺少基于磁盘的存储设备的网络计算机，但包括诸如小型闪存卡的本地永久存储器。 然后，基于磁盘的存储设备将在网络计算机上加载基于磁盘的操作系统。 然后在网络计算机上加载并执行由基于磁盘的操作系统支持的测试套件，以验证其功能。 在一个实施例中，该方法还包括在多个网络计算机中的每一个中类似地安装基于磁盘的存储设备，由此使用单个基于磁盘的存储设备来验证每个多个网络计算机。