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    Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems
    1.
    发明授权
    Method and apparatus to control processor power and performance for single phase lock loop (PLL) processor systems 有权
    用于控制单相锁相环（PLL）处理器系统的处理器功率和性能的方法和装置

    公开(公告)号：US06442697B1

    公开(公告)日：2002-08-27

    申请号：US09534187

    申请日：2000-03-24

    Applicant: Satchit Jain ,  Sun-Soo Cho

    Inventor： Satchit Jain ,  Sun-Soo Cho

    IPC: G06F132

    CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: An integrated circuit contains a central processing unit (“CPU”), a graphic control hub (“GCH”), a memory control hub (“MCH”), and a phase lock loop (“PLL”). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transactions. The PLL is configured to allow the CPU to operate at more than one power consumption states.

    Abstract translation: 集成电路包括中央处理单元（“CPU”），图形控制集线器（“GCH”），存储器控制集线器（“MCH”）和锁相环（“PLL”）。 GCH，MCH和PLL耦合到CPU。 MCH控制内存事务。 PLL被配置为允许CPU以多于一个功耗状态工作。

    Method of initializing a memory controller by executing software in a second memory to wake up a system
    3.
    发明授权
    Method of initializing a memory controller by executing software in a second memory to wake up a system 有权
    通过在第二存储器中执行软件来唤醒系统来初始化存储器控制器的方法

    公开(公告)号：US06782472B2

    公开(公告)日：2004-08-24

    申请号：US10386749

    申请日：2003-03-12

    Applicant: Satchit Jain ,  Sung-Soo Cho

    Inventor： Satchit Jain ,  Sung-Soo Cho

    IPC: G06F9445

    CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/4418 ,  Y02D10/128 ,  Y02D10/171

    Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

    Abstract translation: 系统具有处理器，其具有多个状态，包括唤醒状态和睡眠状态，包括存储器控制器和存储器设备的存储器子系统以及第二存储器。 系统使用第二存储器中的软件来初始化从休眠状态到唤醒状态的存储器控​​制器。 系统检测唤醒事件触发，响应于唤醒事件触发，执行存储在第二存储器中的软件来初始化存储器控制器，然后在初始化之后执行第一存储器中的软件。

    Initializing a memory controller by executing software in second memory to wakeup a system
    4.
    发明授权
    Initializing a memory controller by executing software in second memory to wakeup a system 有权
    通过在第二个内存中执行软件来初始化内存控制器来唤醒系统

    公开(公告)号：US06571333B1

    公开(公告)日：2003-05-27

    申请号：US09434973

    申请日：1999-11-05

    Applicant: Satchit Jain ,  Sung-Soo Cho

    Inventor： Satchit Jain ,  Sung-Soo Cho

    IPC: G06F9445

    CPC classification number: G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  G06F9/4418 ,  Y02D10/128 ,  Y02D10/171

    Abstract: A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

    Abstract translation: 系统具有处理器，其具有多个状态，包括唤醒状态和睡眠状态，包括存储器控制器和存储器设备的存储器子系统以及第二存储器。 系统使用第二存储器中的软件来初始化从休眠状态到唤醒状态的存储器控​​制器。 系统检测唤醒事件触发，响应于唤醒事件触发，执行存储在第二存储器中的软件来初始化存储器控制器，然后在初始化之后执行第一存储器中的软件。

    Entering and exiting power managed states without disrupting accelerated graphics port transactions
    6.
    发明授权
    Entering and exiting power managed states without disrupting accelerated graphics port transactions 有权
    进入和退出电源管理状态，而不会中断加速图形端口事务

    公开(公告)号：US06738068B2

    公开(公告)日：2004-05-18

    申请号：US09751441

    申请日：2000-12-29

    Applicant: Debra T. Cohen ,  Leslie E. Cline ,  Barnes Cooper ,  Satchit Jain ,  Anil V. Nanduri

    Inventor： Debra T. Cohen ,  Leslie E. Cline ,  Barnes Cooper ,  Satchit Jain ,  Anil V. Nanduri

    IPC: G06F1314

    CPC classification number: G06T17/00 ,  G06F1/3203

    Abstract: An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

    Abstract translation: 加速图形端口图形控制器（AGP-GC）和核心控制器之间的接口，以防止进入低功率状态，干扰来自AGP-GC的请求但尚未完成的传输。 核心控制器可以与AGP-GC进行通信，意图进入低功率状态，而AGP-GC可以与核心控制器通信AGP-GC的忙碌状态。 当AGP-GC接收到进入低功率状态的意图时，可以停止向核心控制器发出请求。 当核心控制器检测到AGP-GC正忙时，核心控制器可以推迟进入低功率状态，直到AGP-GC完成任何正在进行的请求。 在接口的替代使用中，如果AGP-GC希望在低功率状态期间发出请求，则可以通过指示忙状态来向核心控制器通知该核心控制器，这可以触发核心控制器发起退出 低功率状态。

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