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公开(公告)号：US20110095925A1
公开(公告)日：2011-04-28
申请号：US12911345
申请日：2010-10-25
IPC分类号： H03M3/00
摘要： In a delta-sigma A/D converter provided with plural channels for converting an analog input signal into a digital signal, an adverse influence of an idle tone is reduced in each channel. The delta-sigma A/D converter comprises: a first quantizer which quantizes and outputs a received signal; a first D/A converter which converts an output signal of the first quantizer into an analog signal, and outputs the converted analog signal; a first operation unit which outputs a signal indicative of a difference of the first analog input signal and an output signal of the first D/A converter; a first integrator which integrates an output signal of the first operation unit and outputs the integrated signal; a first dither circuit which generates a first dither signal; and a second operation unit which adds the first dither signal to the output signal of the first integrator and outputs the added signal to the first quantizer.
摘要翻译： 在具有用于将模拟输入信号转换为数字信号的多个通道的Δ-ΣA / D转换器中，在每个通道中降低了空闲音调的不利影响。 Δ-ΣA / D转换器包括：量化并输出接收信号的第一量化器; 第一D / A转换器，其将第一量化器的输出信号转换为模拟信号，并输出转换的模拟信号; 第一操作单元，其输出表示第一模拟输入信号和第一D / A转换器的输出信号的差的信号; 第一积分器，其对第一运算单元的输出信号进行积分并输出积分信号; 产生第一抖动信号的第一抖动电路; 以及第二操作单元，其将第一抖动信号添加到第一积分器的输出信号，并将相加的信号输出到第一量化器。
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公开(公告)号：US20100296602A1
公开(公告)日：2010-11-25
申请号：US12758624
申请日：2010-04-12
申请人： Fumihiro Inui
发明人： Fumihiro Inui
IPC分类号： H04L27/00
摘要： A signal transmission apparatus that transmits a 1-bit signal obtained by delta-sigma modulation is provided. In the signal transmission apparatus, a pseudo-random noise pattern having a data rate equal to that of the delta-sigma modulated 1-bit signal is generated, and the 1-bit signal is code-modulated using the generated pseudo-random noise pattern. The generated pseudo-random noise pattern and the code-modulated signal obtained through code modulation are transmitted via a transmission line. The transmitted code-modulated signal is demodulated using the transmitted pseudo-random noise pattern.
摘要翻译： 提供发送通过Δ-Σ调制获得的1比特信号的信号发送装置。 在信号发送装置中，生成具有与Δ-Σ调制1位信号相同的数据速率的伪随机噪声模式，并且使用生成的伪随机噪声模式对1位信号进行码调制 。 所产生的伪随机噪声模式和通过码调制获得的码调制信号经由传输线传输。 使用发送的伪随机噪声模式解调发送的码调制信号。
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53.发明授权System-on-chip (SoC) integrated circuit including interleaved delta-sigma analog-to-digital converter (ADC) 有权系统级芯片（SoC）集成电路，包括交错式Δ-Σ模数转换器（ADC）公开(公告)号：US07382300B1
公开(公告)日：2008-06-03
申请号：US11564331
申请日：2006-11-29
IPC分类号： H03M3/00
摘要： A system-on-chip (SoC) integrated circuit including an interleaved delta-sigma analog to digital converter (ADC) provides for reduced noise in the ADC conversions. The ADC is operated intermittently and the balance of the digital circuits forming the system are halted while the conversions take place. The halted portion of the system may include an output low-pass filter of the ADC. The system may include a processor core or other logic having a clock frequency unrelated to the ADC modulator clock frequency that is not otherwise clock-managed to reduce noise induced in the converter output by the operation of the core or other logic.
摘要翻译： 包括交错式Δ-Σ模数转换器（ADC）的片上系统（SoC）集成电路可提供ADC转换中的降低的噪声。 ADC间歇性运行，形成系统的数字电路的平衡在转换发生时停止。 系统的暂停部分可以包括ADC的输出低通滤波器。 该系统可以包括处理器核心或具有与ADC调制器时钟频率无关的时钟频率的其它逻辑，否则不是由时钟管理以便通过核心或其他逻辑的操作来减少在转换器输出中感应的噪声。
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54.发明授权Delta-sigma modulator having quantizer code pattern detection controlled dither 有权具有量化器码模式检测的Delta-sigma调制器控制抖动公开(公告)号：US07317411B1
公开(公告)日：2008-01-08
申请号：US11534195
申请日：2006-09-21
IPC分类号： H03M3/00
摘要： A delta-sigma having quantizer code pattern detection controlled dither reduces the probability of “stuck” code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in modulators that are periodically reset, the pattern detection and dither control reduce the probability of a stuck code sequence at startup. A pattern detection circuit detects a sequence of unchanging quantizer output values and injects a signal at the quantizer input to cause the quantizer to change levels. The injected signal may be a dither signal that is increased in amplitude in response to the detection of unchanging code sequences and then decreased when the quantizer output changes.
摘要翻译： 具有量化器码模式检测控制抖动的Δ-sigma降低了当输入信号和反馈信号相等时发生的“卡”码序列的概率，因此不会发生量化器输出变化。 特别地，在周期性复位的调制器中，模式检测和抖动控制降低了在启动时卡片代码序列的概率。 模式检测电路检测不变量化器输出值的序列，并在量化器输入端注入信号，使量化器变化电平。 注入的信号可以是响应于不变代码序列的检测而在幅度上增加的抖动信号，然后当量化器输出改变时减小。
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公开(公告)号：US07317410B2
公开(公告)日：2008-01-08
申请号：US11340603
申请日：2006-01-27
申请人： Kevin Lee Miller
发明人： Kevin Lee Miller
IPC分类号： H03M1/20
摘要： A digital modulator includes a quantizer and a mapper. The quantizer converts a dithered signal value to a voltage. The mapper provides a modulated signal based on the voltage received from the quantizer. The mapper may maintain a substantially identical average centroid for modulated signals provided by the mapper. In an aspect, the mapper is included in a feedback of the digital modulator. The digital modulator may include any number of mappers. For example, a mode selection switch may select one of a plurality of mappers to map a voltage level received from the quantizer to a respective digital sequence.
摘要翻译： 数字调制器包括量化器和映射器。 量化器将抖动信号值转换为电压。 映射器基于从量化器接收的电压提供调制信号。 映射器可以维持由映射器提供的调制信号的基本相同的平均质心。 在一方面，映射器被包括在数字调制器的反馈中。 数字调制器可以包括任何数量的映射器。 例如，模式选择开关可以选择多个映射器中的一个，以将从量化器接收的电压电平映射到相应的数字序列。
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56.发明授权Method of adding a dither signal in output to the last integrator of a sigma-delta converter and relative sigma-delta converter 有权将输出中的抖动信号添加到Σ-Δ转换器和相对Σ-Δ转换器的最后一个积分器的方法公开(公告)号：US07304592B2
公开(公告)日：2007-12-04
申请号：US11420592
申请日：2006-05-26
申请人： Carlo Pinna , Sergio Pernici , Angelo Nagari
发明人： Carlo Pinna , Sergio Pernici , Angelo Nagari
IPC分类号： H03M3/00
摘要： A single-ended or differential single-stage, or multi-stage sigma-delta analog-to-digital converter includes at least one switched-capacitor integrator comprising a switched-capacitor network receiving as input a signal to be sampled, and an amplifier coupled in cascade to the switched-capacitor network. A circuit is coupled to the amplifier for feeding an analog dither signal to a virtual ground of the amplifier.
摘要翻译： 单端或差分单级或多级Σ-Δ模数转换器包括至少一个开关电容积分器，该开关电容积分器包括接收要被采样的信号作为输入的开关电容器网络，和放大器耦合 级联到开关电容网络。 电路耦合到放大器，用于将模拟抖动信号馈送到放大器的虚拟接地。
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公开(公告)号：US07212142B2
公开(公告)日：2007-05-01
申请号：US10942938
申请日：2004-09-17
申请人： Todd Brooks
发明人： Todd Brooks
IPC分类号： H03M3/00
摘要： Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops. One or more processes are performed in a pipeline having a higher throughput rate than a throughput rate of a delta-sigma modulator. Any of a variety of processes and combinations of processes can be performed in the pipeline including, without limitation, quantization, digital signal processing, and/or feedback digital-to-analog conversion.
摘要翻译： 用于改进Δ-Σ调制器中的反馈处理的方法和系统，包括单位和多位Δ-Σ调制器，连续时间和离散时间Δ-Σ调制器以及数字和/或模拟反馈回路。 在具有比Δ-Σ调制器的吞吐率更高的吞吐速率的流水线中执行一个或多个处理。 可以在流水线中执行各种处理和处理组合中的任何一种，包括但不限于量化，数字信号处理和/或反馈数模转换。
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58.发明申请METHOD OF ADDING A DITHER SIGNAL IN OUTPUT TO THE LAST INTEGRATOR OF A SIGMA-DELTA CONVERTER AND RELATIVE SIGMA-DELTA CONVERTER 有权将信号输入到SIGMA-DELTA转换器和相关SIGMA-DELTA转换器的最后一个整合器的方法公开(公告)号：US20060267823A1
公开(公告)日：2006-11-30
申请号：US11420592
申请日：2006-05-26
申请人： Carlo Pinna , Sergio Pernici , Angelo Nagari
发明人： Carlo Pinna , Sergio Pernici , Angelo Nagari
IPC分类号： H03M3/00
摘要： A single-ended or differential single-stage, or multi-stage sigma-delta analog-to-digital converter includes at least one switched-capacitor integrator comprising a switched-capacitor network receiving as input a signal to be sampled, and an amplifier coupled in cascade to the switched-capacitor network. A circuit is coupled to the amplifier for feeding an analog dither signal to a virtual ground of the amplifier.
摘要翻译： 单端或差分单级或多级Σ-Δ模数转换器包括至少一个开关电容积分器，该开关电容积分器包括接收要被采样的信号作为输入的开关电容器网络，和放大器耦合 级联到开关电容网络。 电路耦合到放大器，用于将模拟抖动信号馈送到放大器的虚拟接地。
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公开(公告)号：US20060125668A1
公开(公告)日：2006-06-15
申请号：US11340603
申请日：2006-01-27
申请人： Kevin Miller
发明人： Kevin Miller
IPC分类号： H03M3/00
摘要： A digital modulator includes a quantizer and a mapper. The quantizer converts a dithered signal value to a voltage. The mapper provides a modulated signal based on the voltage received from the quantizer. The mapper may maintain a substantially identical average centroid for modulated signals provided by the mapper. In an aspect, the mapper is included in a feedback of the digital modulator. The digital modulator may include any number of mappers. For example, a mode selection switch may select one of a plurality of mappers to map a voltage level received from the quantizer to a respective digital sequence.
摘要翻译： 数字调制器包括量化器和映射器。 量化器将抖动信号值转换为电压。 映射器基于从量化器接收的电压提供调制信号。 映射器可以维持由映射器提供的调制信号的基本相同的平均质心。 在一方面，映射器被包括在数字调制器的反馈中。 数字调制器可以包括任何数量的映射器。 例如，模式选择开关可以选择多个映射器中的一个，以将从量化器接收的电压电平映射到相应的数字序列。
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60.发明授权公开(公告)号：US06975255B1
公开(公告)日：2005-12-13
申请号：US10947039
申请日：2004-09-21
申请人： Weibiao Zhang
发明人： Weibiao Zhang
摘要： A dithering method is provided for sigma-delta converters in a deep-submicron process. The dither is a random interleaving of quantizer thresholds levels. The random interleaving dither is more effective than previous static dither methods to remove idle channel tones of sigma-delta analog-to-digital converters (ADC). The dither is easy to implement and takes less area than other dynamic dither methods.
摘要翻译： 在深亚微米工艺中为Σ-Δ转换器提供抖动方法。 抖动是量化器阈值水平的随机交错。 随机交错抖动比先前的静态抖动方法更有效，以去除Σ-Δ模数转换器（ADC）的空闲信道音调。 抖动易于实现，占用的面积比其他动态抖动方法要少。
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