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1.发明授权System-on-chip (SoC) integrated circuit including interleaved delta-sigma analog-to-digital converter (ADC) 有权系统级芯片（SoC）集成电路，包括交错式Δ-Σ模数转换器（ADC）公开(公告)号：US07382300B1
公开(公告)日：2008-06-03
申请号：US11564331
申请日：2006-11-29
IPC分类号： H03M3/00
摘要： A system-on-chip (SoC) integrated circuit including an interleaved delta-sigma analog to digital converter (ADC) provides for reduced noise in the ADC conversions. The ADC is operated intermittently and the balance of the digital circuits forming the system are halted while the conversions take place. The halted portion of the system may include an output low-pass filter of the ADC. The system may include a processor core or other logic having a clock frequency unrelated to the ADC modulator clock frequency that is not otherwise clock-managed to reduce noise induced in the converter output by the operation of the core or other logic.
摘要翻译： 包括交错式Δ-Σ模数转换器（ADC）的片上系统（SoC）集成电路可提供ADC转换中的降低的噪声。 ADC间歇性运行，形成系统的数字电路的平衡在转换发生时停止。 系统的暂停部分可以包括ADC的输出低通滤波器。 该系统可以包括处理器核心或具有与ADC调制器时钟频率无关的时钟频率的其它逻辑，否则不是由时钟管理以便通过核心或其他逻辑的操作来减少在转换器输出中感应的噪声。
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2.发明授权Delta-sigma modulator having quantizer code pattern detection controlled dither 有权具有量化器码模式检测的Delta-sigma调制器控制抖动公开(公告)号：US07317411B1
公开(公告)日：2008-01-08
申请号：US11534195
申请日：2006-09-21
IPC分类号： H03M3/00
摘要： A delta-sigma having quantizer code pattern detection controlled dither reduces the probability of “stuck” code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in modulators that are periodically reset, the pattern detection and dither control reduce the probability of a stuck code sequence at startup. A pattern detection circuit detects a sequence of unchanging quantizer output values and injects a signal at the quantizer input to cause the quantizer to change levels. The injected signal may be a dither signal that is increased in amplitude in response to the detection of unchanging code sequences and then decreased when the quantizer output changes.
摘要翻译： 具有量化器码模式检测控制抖动的Δ-sigma降低了当输入信号和反馈信号相等时发生的“卡”码序列的概率，因此不会发生量化器输出变化。 特别地，在周期性复位的调制器中，模式检测和抖动控制降低了在启动时卡片代码序列的概率。 模式检测电路检测不变量化器输出值的序列，并在量化器输入端注入信号，使量化器变化电平。 注入的信号可以是响应于不变代码序列的检测而在幅度上增加的抖动信号，然后当量化器输出改变时减小。
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3.发明授权Method and system for selecting implementation of a filter controller between a single conversion mode that ensures a fully-settled converted output and a continuous conversion mode 有权用于在确保完全转换的输出和连续转换模式的单个转换模式之间选择滤波器控制器的实现的方法和系统公开(公告)号：US06469650B2
公开(公告)日：2002-10-22
申请号：US09800604
申请日：2001-03-06
申请人： Kartik Nanda , Aryesh Amar , Saibun Wong , Jerome E. Johnston
发明人： Kartik Nanda , Aryesh Amar , Saibun Wong , Jerome E. Johnston
IPC分类号： H03M112
摘要： A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.
摘要翻译： 公开了一种用于在确保完全稳定的转换输出和输入信号的连续转换的单个转换之间选择滤波器控制器的实现的方法和系统。 状态机确定转换开始信号是否具有持续时间，其结束于在输入信号上完成的转换的第一次出现之后或之前。 完成的转换是当从输入信号转换位设置时的出现。 如果转换开始信号具有在第一次完成转换之前或之前结束的持续时间，则状态机选择并实现输入信号的单次转换。 数字系统通过等待滤波器接收和过滤用于转换输出的预定数量的位组，然后输出转换输出，确保完全转换的输出。 否则，状态机选择并实现输入信号的连续转换。
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公开(公告)号：US09563851B2
公开(公告)日：2017-02-07
申请号：US13491212
申请日：2012-06-07
申请人： Jeffrey Bernstein , Benjamin Vigoda , Kartik Nanda , Rishi Chaturvedi , David Hossack , William Peet , Andrew Schweitzer , Timothy Caputo
发明人： Jeffrey Bernstein , Benjamin Vigoda , Kartik Nanda , Rishi Chaturvedi , David Hossack , William Peet , Andrew Schweitzer , Timothy Caputo
摘要： In an aspect, in general, a programmable computation device performs computations of an inference task specified by a plurality of variables and a plurality of factors, each factor being associated with a subset of the variables. The device includes one or more processing elements. Each processing element includes a first storage for a definition of a factor, a second storage for data associated with the inputs and/or outputs of at least some of the computations, and one or more computation units coupled to the first storage and the second storage for performing a succession of parts of the at least some of the computations that are associated with a factor, the succession of parts defined by data in the storage for the definition of the factor.
摘要翻译： 一方面，通常，可编程计算装置执行由多个变量和多个因素指定的推理任务的计算，每个因子与变量的子集相关联。 该装置包括一个或多个处理元件。 每个处理元件包括用于定义因子的第一存储器，用于与至少一些计算的输入和/或输出相关联的数据的第二存储器以及耦合到第一存储器和第二存储器的一个或多个计算单元 用于执行与因素相关联的所述至少一些计算的一部分的连续的部分，所述部分由所述存储器中的数据由所述因子的定义定义的部分所定义。
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公开(公告)号：US20120306569A1
公开(公告)日：2012-12-06
申请号：US13490110
申请日：2012-06-06
申请人： Eric Nestler , Jeffrey Venuti , Vladimir Zlatkovic , Kartik Nanda
发明人： Eric Nestler , Jeffrey Venuti , Vladimir Zlatkovic , Kartik Nanda
IPC分类号： H03K5/00
摘要： An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
摘要翻译： 时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。 将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上，并且输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。 输出由第一和第二阵列的电容器彼此无源耦合确定，并根据耦合的电容器上的总电荷来确定输出。 在一些示例中，在将输出存储在第二电容器阵列之前，将增益应用于总电荷。 在一些示例中，在耦合电容器之前，将电荷量化电路应用于存储在阵列上的电荷以形成输出。
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公开(公告)号：US20090191837A1
公开(公告)日：2009-07-30
申请号：US12241940
申请日：2008-09-30
申请人： Kartik Nanda , John L. Melanson
发明人： Kartik Nanda , John L. Melanson
IPC分类号： H04B1/16
CPC分类号： H02M3/157
摘要： A power control system includes a delta sigma modulator to generate output values for use in controlling a switching power converter. In at least one embodiment, the delta sigma modulator includes two ranges of available output values and a range of one or more unavailable intermediate output values, wherein the range of one or more unavailable intermediate output values represent a gap in available output values. Each unavailable intermediate output value represents an output value that is not generated by the delta sigma modulator. In at least one embodiment, the delta sigma modulator includes a quantizer output remapping module that remaps quantizer output values within the range of one or more unavailable intermediate output values of the delta sigma modulator to new output values within one of the ranges of available output values.
摘要翻译： 功率控制系统包括Δ-Σ调制器以产生用于控制开关功率转换器的输出值。 在至少一个实施例中，ΔΣ调制器包括两个可用输出值范围和一个或多个不可用中间输出值的范围，其中一个或多个不可用中间输出值的范围表示可用输出值中的间隙。 每个不可用的中间输出值表示不由delta-Σ调制器产生的输出值。 在至少一个实施例中，ΔΣ调制器包括量化器输出重映射模块，该量化器输出重映射模块将ΔΣ调制器的一个或多个不可用中间输出值的范围内的量化器输出值重新映射到可用输出值范围内的新输出值 。
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公开(公告)号：US07755525B2
公开(公告)日：2010-07-13
申请号：US12241940
申请日：2008-09-30
申请人： Kartik Nanda , John L. Melanson
发明人： Kartik Nanda , John L. Melanson
IPC分类号： H03M3/00
CPC分类号： H02M3/157
摘要： A power control system includes a delta sigma modulator to generate output values for use in controlling a switching power converter. In at least one embodiment, the delta sigma modulator includes two ranges of available output values and a range of one or more unavailable intermediate output values, wherein the range of one or more unavailable intermediate output values represent a gap in available output values. Each unavailable intermediate output value represents an output value that is not generated by the delta sigma modulator. In at least one embodiment, the delta sigma modulator includes a quantizer output remapping module that remaps quantizer output values within the range of one or more unavailable intermediate output values of the delta sigma modulator to new output values within one of the ranges of available output values.
摘要翻译： 功率控制系统包括Δ-Σ调制器以产生用于控制开关功率转换器的输出值。 在至少一个实施例中，ΔΣ调制器包括两个可用输出值范围和一个或多个不可用中间输出值的范围，其中一个或多个不可用中间输出值的范围表示可用输出值中的间隙。 每个不可用的中间输出值表示不由delta-Σ调制器产生的输出值。 在至少一个实施例中，ΔΣ调制器包括量化器输出重映射模块，该量化器输出重映射模块将ΔΣ调制器的一个或多个不可用中间输出值的范围内的量化器输出值重新映射到可用输出值范围内的新输出值 。
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8.发明授权公开(公告)号：US07750724B2
公开(公告)日：2010-07-06
申请号：US11962022
申请日：2007-12-20
CPC分类号： G05F1/561 , G01R33/0029 , G01R33/07 , G05F3/08
摘要： A temperature and process-stable magnetic field sensor bias current source provides improved performance in Hall effect sensor circuits. A switched-capacitor sensing element is used to sense either a reference current or the bias current directly. A current mirror may be used to generate the bias current from the reference current, and may include multiple current source transistors coupled through corresponding control transistors that are switched using a barrel shifter to reduce variations in the bias current due to process variation. The current mirror control may be provided via a chopper amplifier to reduce flicker noise and the current mirror control voltage may be held using a track/hold circuit during transitions of the chopper amplifier to further reduce noise due to the chopping action.
摘要翻译： 温度和过程稳定的磁场传感器偏置电流源在霍尔效应传感器电路中提供了更好的性能。 开关电容感测元件用于直接感测参考电流或偏置电流。 可以使用电流镜来产生来自参考电流的偏置电流，并且可以包括通过相应的控制晶体管耦合的多个电流源晶体管，所述控制晶体管使用桶形移位器进行切换，以减少由于过程变化引起的偏置电流的变化。 可以经由斩波放大器提供电流镜控制以减少闪烁噪声，并且可以在斩波放大器的转变期间使用轨道/保持电路来保持电流镜控制电压，以进一步减少由于斩波动作引起的噪声。
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9.发明授权Systems and methods for clock mode determination utilizing divide ratio testing 有权使用分频比测试的时钟模式确定的系统和方法公开(公告)号：US07286069B1
公开(公告)日：2007-10-23
申请号：US11136215
申请日：2005-05-24
IPC分类号： H03M1/00
CPC分类号： G06F1/06
摘要： A system for determining a data converter operating mode includes measurement circuitry for measuring master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency and a mapping system for mapping the measurement of the frequency ratio to an operating mode of the data converter. The mapping system generates a set of candidate divide ratios for dividing the master clock frequency to generate corresponding internal master clock frequencies of an internal clock signal and determines the lowest divide ratio which generates a supported internal master clock frequency. In an alternate embodiment, the mapping system determines the divide ratio required by a filter of the data converter by dividing the data clock to master clock frequency ratio by a data clock to internal clock frequency ratio between the data clock frequency and the frequency of an internal clock signal. In additional embodiments, the mapping system gives preference to natural number divide ratios during mode mapping.
摘要翻译： 用于确定数据转换器操作模式的系统包括用于测量主时钟信号的主时钟频率和数据时钟信号的频率与主时钟频率之间的频率比的测量电路和用于映射频率测量的映射系统 与数据转换器的操作模式的比率。 映射系统产生一组候选分频比，用于划分主时钟频率以产生内部时钟信号的相应内部主时钟频率，并确定产生支持的内部主时钟频率的最低分频比。 在替代实施例中，映射系统通过将数据时钟与主时钟频率比除以数据时钟与数据时钟频率与内部频率之间的内部时钟频率比来确定数据转换器的滤波器所需的分频比 时钟信号。 在另外的实施例中，映射系统在模式映射期间优先考虑自然数分配比。
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公开(公告)号：US10097003B2
公开(公告)日：2018-10-09
申请号：US15202659
申请日：2016-07-06
申请人： Kartik Nanda
发明人： Kartik Nanda
摘要： A system for managing delivery of electric power includes at least one source of electric power supplying an aggregate amount of available power and a plurality of electrical loads, each having a priority designation. There is a power management system electrically connected to the source of electrical power and to the plurality of electrical loads. The power management system monitors electrical power demanded by the electrical loads and the aggregate amount of available power of the at least one source of electric power. When the power management system determines that the aggregate demanded power exceeds the aggregate amount of available power, the power management system continues to provide power to each of said electrical loads but at a power level which is less than demanded to one or more of said plurality of electrical loads based on the priority designation of each of said electrical loads.
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