公开(公告)号：US4958308A

公开(公告)日：1990-09-18

申请号：US260835

申请日：1988-10-21

Applicant: Raul Curbelo

Inventor： Raul Curbelo

IPC: H03M1/20

CPC classification number: H03M1/201

Abstract: The present invention provides a technique for improving the resolution of an A/D converter. The input analog signal is sampled to generate an analog level and the analog level is held for an interval. A random noise signal having zero average value is superimposed on the held level to generate a fluctuating voltage. This fluctuating voltage is then sampled a plurality of at least N times, and N sampled values are communicated to the A/D converter so that N digitized values are generated. These digitized values are averaged to provide an output having a digitization error reduced by a factor of N.sup.1/2.

Abstract translation: 本发明提供了一种用于提高A / D转换器的分辨率的技术。 输入模拟信号被采样以产生模拟电平，并且模拟电平保持一段间隔。 将具有零平均值的随机噪声信号叠加在保持电平上以产生波动电压。 然后对该波动电压进行多次采样至少N次，并且将N个采样值传送到A / D转换器，从而生成N个数字化值。 这些数字化值被平均以提供具有减小因子N1 / 2的数字化误差的输出。

公开(公告)号：US4710747A

公开(公告)日：1987-12-01

申请号：US731683

申请日：1985-05-07

Applicant: Alex Holland

Inventor： Alex Holland

IPC: H03M1/00 ,  H03M1/20

CPC classification number: H03M1/201 ,  H03M1/0629 ,  H03M1/0631

Abstract: A system for increasing the accuracy and resolution of an ADC comprising a digital filter connected to the output of the ADC, a system clock for providing a digital filter clock signal, a low/pass filter/amplifier for generating a large-scale, rapidly varying dither signal fdrom the digital filter clock signal, and a summing circuit for adding the dither signal to a test signal connected to the input of the ADC.

Abstract translation: 一种用于提高ADC的精度和分辨率的系统，包括连接到ADC的输出的数字滤波器，用于提供数字滤波器时钟信号的系统时钟，用于产生大规模快速变化的低通/滤波器/放大器 数字滤波器时钟信号的抖动信号，以及用于将抖动信号添加到连接到ADC的输入的测试信号的求和电路。

公开(公告)号：US4543599A

公开(公告)日：1985-09-24

申请号：US498136

申请日：1983-05-25

Applicant: Donald H. Willis ,  Russell T. Fling

Inventor： Donald H. Willis ,  Russell T. Fling

IPC: H03M1/20 ,  H03M1/00 ,  H03K13/01

CPC classification number: H03M1/201 ,  H03M1/361

Abstract: Digital representations of analog signals are limited in resolution accuracy by the number of bits in the digital output signal of an analog-to-digital converter which limits the number of analog output levels produceable by a digital-to-analog converter. The apparent resolution accuracy can be improved, however, by the addition of two "dithering" signals, one at a lower frequency and one at a higher frequency, to increase the number of transitions of the least significant bit (LSB) of the digital signals. In a television receiver employing digital signal processing apparatus, dither signals having magnitudes equivalent to 1/2 and 1/4 LSB and at frequencies related to the TV line frequency and the color subcarrier frequency are preferred.

Abstract translation: 模拟信号的数字表示以分辨率精度限制模数转换器的数字输出信号中的位数，这限制了由数模转换器产生的模拟输出电平的数量。 然而，通过添加两个“抖动”信号，一个在较低频率和一个在较高频率处，可以提高视在分辨率精度，以增加数字信号的最低有效位（LSB）的转换次数 。 在采用数字信号处理装置的电视接收机中，优选具有等于1/2和1/4 LSB的幅度和与TV线频率和彩色副载波频率相关的频率的抖动信号。

公开(公告)号：US4398179A

公开(公告)日：1983-08-09

申请号：US326324

申请日：1981-12-01

Applicant: Shinji Kaneko

Inventor： Shinji Kaneko

IPC: H03M1/20 ,  H03M1/00 ,  H03K13/02

CPC classification number: H03M1/201 ,  H03M1/1215

Abstract: An analog-to-digital converting circuit comprises an input, a clock signal circuit providing first and second clock signals having the same frequency but having a half-cycle phase difference therebetween; first and second analog-to-digital converting stages each having an input coupled to the converting circuit input for receiving an input analog signal, a control terminal for receiving a respective one of the first and second control clock signals, and an output providing an N-bit binary-coded digital signal representing the level of the input analog signal, each having a voltage quantizing interval of .DELTA.V; an output terminal; and a multiplexing circuit, such as a parallel-to-serial converter, for alternately applying to the output terminal the binary coded digital signals of the first and the second analog-to-digital converting stages. In order to achieve greater accuracy, an offset circuit is included to provide to one of the first and the second analog-to-digital converting stages an offset voltage, relative to the other of such stages, of 1/2 .DELTA.V.

Abstract translation: 模数转换电路包括输入端，时钟信号电路，其提供具有相同频率但具有半周期相位差的第一和第二时钟信号; 第一和第二模数转换级，每个转换级具有耦合到转换电路输入的输入端用于接收输入模拟信号的控制端，用于接收第一和第二控制时钟信号中的相应一个的控制端，以及提供N 表示输入模拟信号的电平的每位二进制编码数字信号，每个具有DELTA V的电压量化间隔; 输出端子; 以及诸如并行到串行转换器的多路复用电路，用于交替地向输出端子施加第一和第二模数转换级的二进制编码数字信号。 为了获得更高的精度，包括偏移电路以向第一和第二模数转换级之一提供1/2 DELTA V相对于另一级的偏移电压。

公开(公告)号：US20240364356A1

公开(公告)日：2024-10-31

申请号：US18139779

申请日：2023-04-26

Applicant: Analog Devices International Unlimited Company

Inventor： Asha Ganesan ,  Donald W. Paterson ,  Sharvil Pradeep Patil ,  Nevena Rakuljic

IPC: H03M1/50 ,  H03M1/10 ,  H03M1/20 ,  H03M1/66

CPC classification number: H03M1/50 ,  H03M1/1009 ,  H03M1/201 ,  H03M1/662

Abstract: CT ADCs based on continuous-time residue generation systems require accurate estimation of analog transfer functions. This is done by using a pseudo random bit sequence, injected using a DAC, that traverses the transfer function to be measured. Mismatch in the injection DAC introduces errors in the transfer function estimation and results in poor NSD at the ADC output. Techniques are described to improve the accuracy of the transfer function estimate despite DAC mismatch and despite the presence of an input signal.

公开(公告)号：US20240333296A1

公开(公告)日：2024-10-03

申请号：US18127508

申请日：2023-03-28

Applicant: Avago Technologies International Sales Pte. Limited

Inventor： Yong LIU ,  Wei ZHANG ,  Jun CAO

IPC: H03M1/20 ,  H03M1/18 ,  H03M1/46

CPC classification number: H03M1/201 ,  H03M1/185 ,  H03M1/462

Abstract: A system includes a dither generator module that includes a most significant bits (MSB) dither generator device that generates a first random value. The dither generator module also includes a least significant bits (LSB) dither generator device that generates a second random value. The system further includes a first digital to analog converter (DAC) that receives a sum of the first random value and the second random value and generates a dither signal based on the sum of the first random value and the second random value. The system also includes an analog to digital converter (ADC) that receives a sum of the dither signal and a sampled input signal and generates a first digitized signal. The system includes a subtraction module that subtracts the sum of the first random value and the second random value from the first digitized signal to produce a digitized output signal.

公开(公告)号：US11791830B2

公开(公告)日：2023-10-17

申请号：US18062623

申请日：2022-12-07

Applicant: Halo Microelectronics International

Inventor： Lijie Zhao ,  Kien Chan Vi ,  Hai Tao

IPC: H03M1/06 ,  H03M1/20 ,  H03M1/46 ,  H03M1/40

CPC classification number: H03M1/0607 ,  H03M1/201 ,  H03M1/40 ,  H03M1/46

Abstract: An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N−K)th capacitor, and a constant binary weight from the (N−K)th capacitor to a (N−K−2+2(K+1))th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2(K+1) steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

公开(公告)号：US11728819B2

公开(公告)日：2023-08-15

申请号：US17555270

申请日：2021-12-17

Applicant: Lawrence Livermore National Security, LLC

Inventor： Brandon Walter Buckley ,  Ryan Douglas Muir

IPC: H03M1/20

CPC classification number: H03M1/201

Abstract: Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a time-varying dither signal, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein each waveform has a waveform duration, wherein an average of the time-varying dither signal over multiple waveform durations is substantially zero, and wherein the time-varying dither signal varies over each waveform duration, generating a timing alignment, combining each waveform with the corresponding portion of the time-varying dither signal over each waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal, wherein the timing alignment is used to align the multiple instances of the waveform in the analog output signal.

公开(公告)号：US20170279458A1

公开(公告)日：2017-09-28

申请号：US15504150

申请日：2015-09-25

Applicant: Continental Teves AG & Co.oHG

Inventor： Heinrich Acker

IPC: H03M1/06 ,  H03M1/60 ,  H03M1/00 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/0626 ,  H03M1/002 ,  H03M1/0614 ,  H03M1/1009 ,  H03M1/124 ,  H03M1/201 ,  H03M1/60

Abstract: A device for digitizing an analogue signal, wherein a distortion signal outlet of a distortion signal generator is only coupled to an analogue digital converter by passive components.

公开(公告)号：US09667267B2

公开(公告)日：2017-05-30

申请号：US15121381

申请日：2015-01-28

Applicant: China Electronic Technology Corporation, 24th Research Institute

Inventor： Yan Wang ,  Gang-Yi Hu ,  Tao Liu ,  Yu-Xin Wang ,  Jian-An Wang ,  Dong-Bing Fu ,  Ting Li ,  Guang-Bing Chen

IPC: H03M1/20 ,  H03M1/10 ,  H03M1/12 ,  H03M1/46 ,  H03M1/06 ,  H03M1/74

CPC classification number: H03M1/201 ,  H03M1/0641 ,  H03M1/1009 ,  H03M1/1061 ,  H03M1/1245 ,  H03M1/46 ,  H03M1/742

Abstract: A dither circuit for high-resolution analog-to-digital converters (ADCs) is presented, including a settable pseudorandom sequence generator, a trimming module, a trimmable digital-to-analog conversion circuit, a dither introduced circuit and a dither elimination circuit, wherein the settable pseudorandom sequence generator works to generate pseudorandom sequence signal uncorrelated to analog input signal and its output can be set, of which n bit output is taken as digital dither signal and n can be less than the quantization bit of the ADC; the trimming module works to determine the trimming signals for the trimmable digital-to-analog conversion circuit to convert the digital dither signal into analog dither signal precisely; the dither introduced circuit works to introduce the analog dither signal to the ADC; the dither elimination circuit works to remove the digital dither signal from the output of ADC. The dither circuit features less complexity and better dynamic performance for high-resolution ADC.