公开(公告)号：US20110057703A1

公开(公告)日：2011-03-10

申请号：US12877575

申请日：2010-09-08

申请人： Tomohiko Kamatani

发明人： Tomohiko Kamatani

IPC分类号： H03L5/00

CPC分类号： H03K5/084 ,  G06F1/3296 ,  Y02D10/172

摘要： A semiconductor device includes an internal circuit to perform a predetermined function at a plurality of different supply power voltages, a power supply voltage region detector to detect a supply power voltage to output a detection signal, a latch to store the signal output from the power supply voltage region detector and output the stored signal as a power supply voltage region signal, and a reset circuit to generate a reset signal to perform a predetermined reset operation on the internal circuit. The latch stores the output signal from the power supply voltage region detector just after the reset operation for the internal circuit is released, and the internal circuit changes an internal setting according to the power supply voltage region signal output from the latch.

摘要翻译： 半导体器件包括在多个不同电源电压下执行预定功能的内部电路，用于检测供电电压以输出检测信号的电源电压区域检测器，用于存储从电源输出的信号的锁存器 电压区域检测器，并将存储的信号作为电源电压区域信号输出，以及复位电路，以产生复位信号，以对内部电路执行预定的复位操作。 在内部电路的复位操作被解除之后，锁存器存储来自电源电压区域检测器的输出信号，并且内部电路根据从锁存器输出的电源电压区域信号改变内部设置。

公开(公告)号：US07663421B2

公开(公告)日：2010-02-16

申请号：US11902348

申请日：2007-09-20

申请人： Robert Schilling

发明人： Robert Schilling

IPC分类号： H03L5/00

CPC分类号： H03K3/02337 ,  H03K5/084 ,  H03K17/691 ,  H03K17/78 ,  H03K2217/0036

摘要： An electronic circuit arrangement is disclosed for converting an input voltage signal having a first voltage level into an output signal having a second voltage level. An input unit is provided for inputting the input voltage signal at the first voltage level, while an output unit is arranged for outputting the output signal at the output of the electronic circuit arrangement. A threshold value comparison unit serves for comparing the first voltage level of the input signal with a switch-on threshold value. The circuit arrangement furthermore contains an input impedance changeover unit for changing over an input impedance of the circuit arrangement from a low value to a high value after a predetermined delay duration after the first voltage level of the input voltage signal exceeded the switch-on threshold value.

摘要翻译： 公开了一种用于将具有第一电压电平的输入电压信号转换成具有第二电压电平的输出信号的电子电路装置。 提供输入单元，用于在第一电压电平输入输入电压信号，而输出单元被布置用于在电子电路装置的输出处输出输出信号。 阈值比较单元用于将输入信号的第一电压电平与接通阈值进行比较。 所述电路装置还包括输入阻抗转换单元，用于在所述输入电压信号的所述第一电压电平超过所述接通阈值之后的预定延迟持续时间之后将所述电路装置的输入阻抗从低值切换到高电平值 。

公开(公告)号：US07372342B2

公开(公告)日：2008-05-13

申请号：US11461155

申请日：2006-07-31

申请人： Michael Berens

发明人： Michael Berens

IPC分类号： H03B5/36

CPC分类号： H03B5/36 ,  H03K5/084

摘要： A high-performance crystal oscillator providing effective bias resistors with low power consumption and minimal substrate surface area. In various embodiments of the invention, a switched-capacitor resistor is operably coupled to circuit components, such as an oscillation source, a current source, an input buffer, or an amplifier to provide a bias resistance.

摘要翻译： 提供低功耗和最小衬底表面积的有效偏置电阻的高性能晶体振荡器。 在本发明的各种实施例中，开关电容电阻器可操作地耦合到电路部件，例如振荡源，电流源，输入缓冲器或放大器以提供偏置电阻。

公开(公告)号：US20080042770A1

公开(公告)日：2008-02-21

申请号：US11461155

申请日：2006-07-31

申请人： Michael Berens

发明人： Michael Berens

IPC分类号： H03L7/099

CPC分类号： H03B5/36 ,  H03K5/084

摘要： A high-performance crystal oscillator providing effective bias resistors with low power consumption and minimal substrate surface area. In various embodiments of the invention, a switched-capacitor resistor is operably coupled to circuit components, such as an oscillation source, a current source, an input buffer, or an amplifier to provide a bias resistance.

摘要翻译： 提供低功耗和最小衬底表面积的有效偏置电阻的高性能晶体振荡器。 在本发明的各种实施例中，开关电容电阻器可操作地耦合到电路部件，例如振荡源，电流源，输入缓冲器或放大器以提供偏置电阻。

公开(公告)号：US20060197608A1

公开(公告)日：2006-09-07

申请号：US11069664

申请日：2005-03-01

申请人： Hector Sanchez ,  Carlos Greaves ,  Jim Nissen ,  Xinghai Tang

发明人： Hector Sanchez ,  Carlos Greaves ,  Jim Nissen ,  Xinghai Tang

IPC分类号： H03L7/00

CPC分类号： H03L7/0995 ,  H03K3/0377 ,  H03K5/084 ,  H03K5/133 ,  H03K2005/00071 ,  H03L7/0896

摘要： A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

公开(公告)号：US20050184782A1

公开(公告)日：2005-08-25

申请号：US11018275

申请日：2004-12-21

申请人： Manoj Sharma ,  Sunil Kasanyal ,  Rajesh Narwal

发明人： Manoj Sharma ,  Sunil Kasanyal ,  Rajesh Narwal

IPC分类号： H03K3/3565 ,  H03K5/08 ,  H04L25/02 ,  H03K3/037

CPC分类号： H04L25/0292 ,  H03K3/3565 ,  H03K5/084 ,  H04L25/0272

摘要： The differential input receiver provides constant symmetrical hysteresis over a wide input signal range. The differential input receiver includes a pair of complementary differential comparators having common input terminals, a pair of series connected complementary current mirrors each having source terminals driven by the output terminals of the corresponding differential comparator, a pair of transistors connected in series across each differential pair transistor in each differential comparator to form a potential divider across it, and a pair of series connected inverting buffers connected to a common output of the differential comparators to provide the final output. The individual buffer outputs are fed back to the control terminals of the series connected transistors in a manner that provides positive feedback thereby providing equal rise-time, fall-delay and transition times in the output signal.

摘要翻译： 差分输入接收器在宽输入信号范围内提供恒定的对称滞后。 差分输入接收机包括一对具有公共输入端的互补差分比较器，一对串联连接的互补电流镜，每个具有由相应的差分比较器的输出端驱动的源极端子，一对晶体管串联连接在每个差分对上 晶体管在每个差分比较器中形成分压器，并且一对串联连接的反相缓冲器连接到差分比较器的公共输出端以提供最终输出。 单个缓冲器输出以提供正反馈的方式反馈到串联连接的晶体管的控制端，从而在输出信号中提供相等的上升时间，下降延迟和转换时间。

公开(公告)号：US06111443A

公开(公告)日：2000-08-29

申请号：US10895

申请日：1998-01-22

申请人： Robert Mores ,  Harald Eisele

发明人： Robert Mores ,  Harald Eisele

IPC分类号： H03K5/08 ,  H03K3/356 ,  H03K17/04

CPC分类号： H03K5/088 ,  H03K5/084

摘要： Generally speaking, steep signal edges are required for the processing of digital signals; however, notably externally supplied signals which are conducted, for example, via long cables are liable to have comparatively flat signal edges. By selecting appropriate switching thresholds, delays between an input signal and an output signal of a circuit can be minimized. The circuit selects the first switching threshold at a low value of the input signal and switches the first threshold value to a second, higher threshold value when the input signal exceeds a further, higher threshold value. Thus, an output signal is generated comparatively quickly after the beginning of the positive-going or negative-going edge of the input signal. This can be realized by switching over the switching threshold of a comparator or by utilizing two comparators. Switching over to the various switching thresholds, or the various comparators, is provided by a further control circuit which may also be driven by the comparators themselves. A particularly high insensitivity to interference is achieved when use is made of two comparators which themselves are constructed as Schmitt triggers.

摘要翻译： 一般来说，数字信号的处理需要陡峭的信号边缘; 然而，特别是例如通过长电缆传导的外部提供的信号易于具有相对平坦的信号边缘。 通过选择适当的切换阈值，可以最小化输入信号和电路的输出信号之间的延迟。 该电路以输入信号的低值选择第一切换阈值，并且当输入信号超过更高阈值时将第一阈值切换到第二阈值。 因此，在输入信号的正向或反向沿的开始之后，相对较快地产生输出信号。 这可以通过切换比较器的切换阈值或利用两个比较器来实现。 切换到各种切换阈值或各种比较器由另外的控制电路提供，该控制电路也可以由比较器本身驱动。 当使用两个本身构造为施密特触发器的比较器时，实现了对干扰特别高的不敏感性。

公开(公告)号：US6084433A

公开(公告)日：2000-07-04

申请号：US55105

申请日：1998-04-03

申请人： Afshin D. Momtaz

发明人： Afshin D. Momtaz

IPC分类号： G06F13/40 ,  H03K5/08 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K3/356 ,  H03K5/22

CPC分类号： H03K5/084 ,  G06F13/4072 ,  H03K19/0027 ,  H03K19/00384

摘要： A high-speed SCSI input receiver has separate high and low level input buffers, each operating in response to a control voltage that conditions their respective high and low level switching threshold voltages to remain stable about their design values without regard to temperature and process parameter variations. Each of the input buffers includes an input invertor with n-channel and p-channel current source transistors coupled between the output and the respective supply rails. A master circuit includes circuitry that substantially matches the operative circuitry of the input buffer, except that the input and output of the master circuit's invertor element are coupled together so as to define the elements actual switching threshold voltage. This threshold voltage is compared to a design threshold voltage defined by a resistor divider in a comparator. The comparator output defines a control voltage which drives the n-channel and p-channel current source transistors until the actual switching threshold voltage of the master circuit's invertor equals the design switching threshold voltage defined by the resistor divider. The control voltage is parallel connected to the n-channel and p-channel current source transistors of the input buffer which causes the input buffer to exhibit an actual switching threshold voltage substantially equal to the design switching threshold voltage without regard to variations in temperature and process parameter tolerances.

公开(公告)号：US6046611A

公开(公告)日：2000-04-04

申请号：US89452

申请日：1998-06-03

申请人： Chikayoshi Morishima

发明人： Chikayoshi Morishima

IPC分类号： H03K17/04 ,  H03K5/153 ,  H03K19/0944

CPC分类号： H03K5/084 ,  H03K5/1252 ,  H03K5/2481 ,  H04L25/0296

摘要： A delay circuit (7) delays a transfer signal (V1) transferred through a transfer signal line (1) by the first delay time (dt1) to generate the first delayed signal (V9) and delays the first delayed signal (V9) by the second delay time (dt2) to generate the second delayed signal (V10). The second current mirror differential amplifier circuit (11) receives the transfer signal (1) and the second delayed signal (V10), whose ground terminal is connected to the first delayed signal line (9). On the other hand, the first current mirror differential amplifier circuit (14) also receives the transfer signal (V1) and the second delayed signal (V10), whose power-supply terminal is connected to the first delayed signal line (9). In response to a rise of the input signal (V1), the circuit (14) starts its operation to change a level of an output signal (V6) from "L" level to "H" level, remaining thereafter. After that, in response to a fall of the input signal (V1), the circuit (11) starts its operation to change the level of the output signal (V6) from "H" level to "L" level. With this configuration, a receiver circuit of a semiconductor circuit device achieves a faster operation and a lower power consumption.

摘要翻译： 延迟电路（7）将通过传送信号线（1）传送的传送信号（V1）延迟第一延迟时间（dt1）以产生第一延迟信号（V9），并将第一延迟信号（V9）延迟 第二延迟时间（dt2）以产生第二延迟信号（V10）。 第二电流镜差分放大器电路（11）接收其接地端子连接到第一延迟信号线（9）的传输信号（1）和第二延迟信号（V10）。 另一方面，第一电流镜差分放大器电路（14）还接收其电源端子连接到第一延迟信号线（9）的传输信号（V1）和第二延迟信号（V10）。 响应于输入信号（V1）的上升，电路（14）开始其操作，以将输出信号（V6）的电平从“L”电平改变为“H”电平，此后剩余。 之后，响应于输入信号（V1）的下降，电路（11）开始其操作，以将输出信号（V6）的电平从“H”电平改变为“L”电平。 利用这种配置，半导体电路器件的接收器电路实现更快的操作和更低的功耗。

公开(公告)号：US5635911A

公开(公告)日：1997-06-03

申请号：US438946

申请日：1995-05-11

申请人： David J. Landers ,  Gregry C. Miller ,  Kevin P. McEnaney ,  Scott A. Holmstrom

发明人： David J. Landers ,  Gregry C. Miller ,  Kevin P. McEnaney ,  Scott A. Holmstrom

IPC分类号： G06M1/10 ,  G06M7/00 ,  H03K5/08 ,  G08B21/00

CPC分类号： H03K5/084 ,  A01C7/105 ,  G06M1/101 ,  G06M7/00 ,  Y10S111/903 ,  Y10S706/90

摘要： An apparatus and method for accurately counting the number of articles passing along an article path. A light beam is transmitted across an article path to a sensor, which light beam is interfered with by the passage of articles along the article path and the received light beam is converted to electrical signals that are conditioned, amplified and input to a logic unit which, based on derived amplitude, duration and area of the input signals, determines the number of articles that passed along the article path. A system is also described which accurately counts the number of articles passing along a plurality of article paths by employing a plurality of such devices each of which accurately counts the articles passing along each article path and, upon instructions from a master console, sends its counts to the master console for summation. The system further includes a network architecture with simplified wire harnessing and enhanced operation.

摘要翻译： 一种用于准确地计数沿物品路径通过的物品数量的装置和方法。 光束穿过物品路径传输到传感器，该光束通过物品沿着物品路径的通过而被干扰，并且接收的光束被转换成被调节，放大并输入到逻辑单元的电信号，该逻辑单元 基于导出的幅度，持续时间和输入信号的面积，确定沿着物品路径传递的物品的数量。 还描述了一种系统，其通过采用多个这样的装置来精确地计数通过多个物品路径的物品的数量，每个这样的装置精确地计数沿着每个物品路径传递的物品，并且根据主控制台的指示发送其计数 到主控台进行求和。 该系统还包括具有简化的线束和增强的操作的网络架构。