Integrated circuit SCSI input receiver having precision high speed input
buffer with hysteresis
摘要:
A high-speed SCSI input receiver has separate high and low level input buffers, each operating in response to a control voltage that conditions their respective high and low level switching threshold voltages to remain stable about their design values without regard to temperature and process parameter variations. Each of the input buffers includes an input invertor with n-channel and p-channel current source transistors coupled between the output and the respective supply rails. A master circuit includes circuitry that substantially matches the operative circuitry of the input buffer, except that the input and output of the master circuit's invertor element are coupled together so as to define the elements actual switching threshold voltage. This threshold voltage is compared to a design threshold voltage defined by a resistor divider in a comparator. The comparator output defines a control voltage which drives the n-channel and p-channel current source transistors until the actual switching threshold voltage of the master circuit's invertor equals the design switching threshold voltage defined by the resistor divider. The control voltage is parallel connected to the n-channel and p-channel current source transistors of the input buffer which causes the input buffer to exhibit an actual switching threshold voltage substantially equal to the design switching threshold voltage without regard to variations in temperature and process parameter tolerances.
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