公开(公告)号：US07783035B2

公开(公告)日：2010-08-24

申请号：US11612438

申请日：2006-12-18

申请人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

发明人： Todd Sperry ,  Sivakumar Munnangi ,  Shridhar Mukund

IPC分类号： H04L9/00 ,  G06F15/16

CPC分类号： F04D29/703 ,  F04D29/388

摘要： A network node is disclosed. The network node includes a host processor. The network node also includes an integrated circuit. The integrated circuit includes a hardware portion configured to perform a first set of TCP acceleration tasks that require a first speed level. The integrated circuit also includes a network protocol processor configured to perform a second set of TCP acceleration tasks that require a second speed level, which is lower than the first speed level. The integrated circuit further includes an embedded processor configured to perform a third set of TCP acceleration tasks that require a third speed level, which is lower than the second speed level. The network node further includes a plurality of data paths configured to couple the integrated circuit to the host processor, the plurality of data paths being implemented based on different protocols.

摘要翻译： 公开了一种网络节点。 网络节点包括主机处理器。 网络节点还包括集成电路。 集成电路包括被配置为执行需要第一速度级别的第一组TCP加速任务的硬件部分。 集成电路还包括被配置为执行第二组TCP加速任务的网络协议处理器，其需要低于第一速度级别的第二速度级别。 集成电路还包括被配置为执行需要低于第二速度级别的第三速度级别的第三组TCP加速任务的嵌入式处理器。 网络节点还包括被配置为将集成电路耦合到主处理器的多个数据路径，所述多个数据路径是基于不同协议来实现的。

公开(公告)号：US07743308B2

公开(公告)日：2010-06-22

申请号：US11350079

申请日：2006-02-09

申请人： Sanjay Subbarao

发明人： Sanjay Subbarao

IPC分类号： G11C29/00

CPC分类号： G06F11/1076 ,  G06F2211/1054

摘要： A method and system for generating parity symbols and rebuilding data symbols in a RAID system. The method includes receiving a command to generate a desired parity or data symbol using an XOR relationship between some of a plurality of parity and data symbols. A symbol of the plurality of parity and data symbols is input to an XOR accumulator, the symbol being included in the XOR relationship. Additional symbols of the plurality of parity and data symbols are input to the XOR accumulator. Each time that an additional symbol is input and is included in the XOR relationship, an XOR operation is performed between the symbol in the XOR accumulator and the additional symbol, thus obtaining a resulting symbol that replaces the previous symbol in the XOR accumulator. After every symbol included in the XOR relationship has undergone an XOR operation, the symbol in the XOR accumulator is output as the desired parity or data symbol.

摘要翻译： 用于在RAID系统中产生奇偶校验符号和重建数据符号的方法和系统。 该方法包括使用多个奇偶校验和数据符号中的一些之间的XOR关系来接收生成期望的奇偶校验或数据符号的命令。 将多个奇偶校验和数据符号的符号输入到XOR累加器，该符号被包括在XOR关系中。 将多个奇偶校验和数据符号的附加符号输入到XOR累加器。 每次输入附加符号并且被包括在XOR关系中时，在XOR累加器中的符号和附加符号之间执行异或运算，从而获得取代XOR累加器中的先前符号的结果符号。 在XOR关系中包含的每个符号经过异或运算后，XOR累加器中的符号将作为所需的奇偶校验或数据符号输出。

公开(公告)号：US07711793B1

公开(公告)日：2010-05-04

申请号：US10665846

申请日：2003-09-17

申请人： Andrew W. Wilson

发明人： Andrew W. Wilson

IPC分类号： G06F15/16 ,  G06F13/00

CPC分类号： G06F11/2089 ,  G06F2201/85

摘要： A method for storing data is provided which includes transmitting a storage operation request to one of at least two controllers where the at least two controllers is capable of managing communication with a plurality of targets. The method further includes directing the storage operation request to an operational one of the at least two controllers when the one of the at least two controllers is inoperable. The method also includes processing the storage operation request with the operational one of the at least two controllers.

摘要翻译： 提供了一种用于存储数据的方法，其包括向至少两个控制器中的至少两个控制器之一发送存储操作请求，其中至少两个控制器能够管理与多个目标的通信。 该方法还包括当至少两个控制器中的一个不可操作时，将存储操作请求定向到至少两个控制器中的可操作的一个。 该方法还包括利用至少两个控制器中的可操作的一个处理存储操作请求。

公开(公告)号：US07698625B2

公开(公告)日：2010-04-13

申请号：US10925170

申请日：2004-08-25

申请人： Robert L. Horn

发明人： Robert L. Horn

IPC分类号： H03M13/00

CPC分类号： G06F11/1076 ,  G06F2211/1054 ,  G06F2211/1057

摘要： A dual parity hardware architecture that enables data to be read from each sector only once and performs both the P parity and Q parity from the single data source. The Q parity calculator provides parallel processing capabilities so that multiple parity operations are performed on the same sector simultaneously. The dual parity hardware architecture provides flexibility in restoring data, generating parity, and updating parity for differing data sector sizes.

摘要翻译： 双奇偶校验硬件架构，使数据只能从每个扇区读取一次，并从单个数据源执行P奇偶校验和Q奇偶校验。 Q奇偶校验计算器提供并行处理能力，使得同时在同一扇区上执行多个奇偶校验操作。 双奇偶校验硬件架构提供恢复数据，生成奇偶校验和更新不同数据扇区大小的奇偶校验的灵活性。

公开(公告)号：US07509473B2

公开(公告)日：2009-03-24

申请号：US10778149

申请日：2004-02-17

申请人： Robert L. Horn ,  Virgil V. Wilkins

发明人： Robert L. Horn ,  Virgil V. Wilkins

IPC分类号： G06F12/00 ,  G06F12/10

CPC分类号： G06F3/0664 ,  G06F3/0607 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0689

摘要： A system for mapping between logical addresses and storage units of a plurality of storage volumes which comprise a storage system. For each volume, logical addresses are mapped to storage units using a volume mapping table. Each volume mapping table is comprised of a plurality of segments. Each segment need not be contiguously allocated to another segment of the same table. Thus, each volume mapping table can be independently expanded or reduced without affecting other volume mapping tables. A hash function, a hash table, a segment table, and a redundancy group descriptor table may also be used to help manage the segments of the volume mapping tables.

摘要翻译： 用于在包括存储系统的多个存储卷的逻辑地址和存储单元之间进行映射的系统。 对于每个卷，使用卷映射表将逻辑地址映射到存储单元。 每个卷映射表由多个段组成。 每个段不需要连续地分配给同一个表的另一个段。 因此，可以独立地扩展或缩小每个卷映射表，而不影响其他卷映射表。 散列函数，哈希表，段表和冗余组描述符表也可以用于帮助管理卷映射表的段。

公开(公告)号：US07502459B1

公开(公告)日：2009-03-10

申请号：US10086270

申请日：2002-02-28

申请人： Edward Moseley

发明人： Edward Moseley

IPC分类号： H04M3/00

CPC分类号： G06Q10/08 ,  G06Q10/06311 ,  G06Q30/016 ,  H04M3/523

摘要： A system, method and apparatus for determining a support entitlement level are provided. A product support request is received from a customer. A technical support identification (TSID) is also received from the customer. The TSID is validated and classified. The TSID may be classified into at least one of several classifications. One of the classifications is a contract classification. At least one of several support levels are assigned to the classified TSID. The assigned support level corresponds to the TSID classification. The TSID is received, validated, classified and the support level assigned before a product support agent is notified of the product support request. Then the assigned support level is delivered.

摘要翻译： 提供了一种用于确定支持权利级别的系统，方法和装置。 从客户处收到产品支持请求。 还收到了客户的技术支持识别（TSID）。 TSID验证和分类。 TSID可以分为几个分类中的至少一个。 其中一个分类是合同分类。 将多个支持级别中的至少一个分配给分类的TSID。 分配的支持级别对应于TSID分类。 接收，验证，分类TSID，并在产品支持代理被通知产品支持请求之前分配的支持级别。 然后交付分配的支持级别。

公开(公告)号：US07484017B1

公开(公告)日：2009-01-27

申请号：US11170293

申请日：2005-06-28

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F9/30

CPC分类号： G06F13/385

摘要： A two-dimensional command block queue includes a plurality of command blocks in a first linked list. One of the command blocks in a string is included in the first linked list. The string is delimited by only a tail pointer stored in a tail pointer list. Following dequeuing the string for processing, a pointer to the one command block of the string that was in the common queue is included in a string head pointer list. The tail pointer to the string is not changed in the tail pointer list following dequeuing of the string. This allows any new SCBs to be appended to the end of the string, while the string is being processed. This allows streaming of new SCBs to an I/O device that had previously been selected and is still connected to the host adapter.

摘要翻译： 二维命令块队列包括第一链表中的多个命令块。 字符串中的一个命令块包含在第一个链表中。 字符串仅由尾部指针列表中存储的尾部指针分隔。 在列出要处理的字符串之后，指向公共队列中的字符串的一个命令块的指针包含在字符串头指针列表中。 在字符串出列之后，尾部指针列表中没有改变字符串的尾部指针。 这样可以在处理字符串时，将任何新的SCB追加到字符串的末尾。 这允许将新的SCB流传输到先前已被选择并仍连接到主机适配器的I / O设备。

公开(公告)号：US07406619B2

公开(公告)日：2008-07-29

申请号：US11088395

申请日：2005-03-23

申请人： William E. Lynn

发明人： William E. Lynn

IPC分类号： G06F11/00

CPC分类号： G06F3/0658 ,  G06F3/0626 ,  G06F3/0689 ,  G06F12/0866

摘要： A RAID system includes a pair of RAID controllers adapted to operate in active-active mode, each controller including a cache memory and at least one SAS/SATA I/O chip connected to a plurality of hard disk drives. Each SAS/SATA I/O chip includes more SAS/SATA ports than required to carry data to the hard drives. The caches in the respective controllers are synchronized via the extra SAS/SATA ports in each controller.

摘要翻译： RAID系统包括适于在主动 - 主动模式下操作的一对RAID控制器，每个控制器包括缓存存储器和连接到多个硬盘驱动器的至少一个SAS / SATA I / O芯片。 每个SAS / SATA I / O芯片包括比将数据传输到硬盘驱动器所需的更多SAS / SATA端口。 各个控制器中的缓存通过每个控制器中的额外SAS / SATA端口进行同步。

公开(公告)号：US07324421B1

公开(公告)日：2008-01-29

申请号：US10218313

申请日：2002-08-13

申请人： Barry Allen Davis ,  Walter F. Bridgewater

发明人： Barry Allen Davis ,  Walter F. Bridgewater

IPC分类号： G11B11/00

CPC分类号： H03K5/135 ,  H04L7/0337

摘要： An invention is provided for data bit align. The invention includes a multiplexer that receives a data sample word as data input and also receives a clock sample word as select input. The multiplexer selects a data bit from the data sample word based on the clock sample word. Generally, the multiplexer can select the data bit from the data sample word corresponding to a position of the clock edge in the clock sample word. The invention also includes an output register, which is coupled to the multiplexer. The output register stores the selected data bit from the multiplexer and provides the selected data bit to remaining system components.

摘要翻译： 提供了一种用于数据位对齐的发明。 本发明包括接收数据采样字作为数据输入并且还接收时钟采样字作为选择输入的多路复用器。 多路复用器根据时钟采样字从数据采样字中选择一个数据位。 通常，多路复用器可以从对应于时钟采样字中的时钟沿的位置的数据采样字中选择数据位。 本发明还包括耦合到多路复用器的输出寄存器。 输出寄存器从多路复用器存储所选择的数据位，并将选定的数据位提供给剩余的系统组件。

公开(公告)号：US07305603B1

公开(公告)日：2007-12-04

申请号：US10762799

申请日：2004-01-21

申请人： Ross Stenfort

发明人： Ross Stenfort

IPC分类号： G01R31/28 ,  G06K5/04

CPC分类号： G01R31/318541

摘要： An apparatus for performing a boundary scan test is provided, along with method for integrating and operating the same. The apparatus includes an asynchronous flip-flop that has a data input, a data output, a system clock input, a set input, and a reset input. The apparatus also includes a test controller that has a test clock input, a first test data output, and a second test data output. The first test data output of the test controller is connected to the set input of the asynchronous flip-flop. In addition, the second test data output of the test controller is connected to the reset input of the asynchronous flip-flop. The test controller is configured to control the asynchronous flip-flop through the set input and the reset input. The apparatus for performing the boundary scan test avoids introduction of adverse delay and skew effects caused by multiplexing circuitry.

摘要翻译： 提供了一种用于执行边界扫描测试的装置，以及用于集成和操作边界扫描测试的方法。 该装置包括具有数据输入，数据输出，系统时钟输入，设定输入和复位输入的异步触发器。 该装置还包括具有测试时钟输入，第一测试数据输出和第二测试数据输出的测试控制器。 测试控制器的第一个测试数据输出连接到异步触发器的设定输入。 此外，测试控制器的第二测试数据输出连接到异步触发器的复位输入。 测试控制器配置为通过设置输入和复位输入来控制异步触发器。 用于执行边界扫描测试的装置避免引入由复用电路引起的不利的延迟和偏斜效应。