公开(公告)号：US06871238B1

公开(公告)日：2005-03-22

申请号：US10779416

申请日：2004-02-12

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F3/06 ,  G06F11/20 ,  G06F13/00 ,  H04B1/74 ,  H04L1/22 ,  H05K10/00

CPC分类号： G06F11/2087 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0689 ,  Y10S707/99953 ,  Y10S707/99955

摘要： A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

摘要翻译： 单个主机适配器硬件I / O控制块包含用于指定从主机系统到第一目标设备的数据传输的信息，以及指定是否要镜像数据的信息，如果是，则可选地识别第二个 要在其上镜像数据的目标设备。 将单个硬件I / O控制块传输到主机适配器集成电路后，主机适配器集成电路确定硬件I / O控制块是否指定镜像事务。 如果指定了镜像事务，则主机适配器集成电路使用第一个硬件I / O控制块中的信息为第二个目标设备生成第二个硬件I / O控制块。 当两个硬件I / O控制块的执行完成时，主机适配器集成电路向主机系统提供单个完成通知。

公开(公告)号：US06862631B1

公开(公告)日：2005-03-01

申请号：US10779351

申请日：2004-02-12

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F3/06 ,  G06F11/20 ,  G06F12/00 ,  G06F12/16 ,  G06F13/28 ,  H04B1/74

CPC分类号： G06F11/2087 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0689 ,  Y10S707/99953 ,  Y10S707/99955

摘要： A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

摘要翻译： 单个主机适配器硬件I / O控制块包含用于指定从主机系统到第一目标设备的数据传输的信息，以及指定是否要镜像数据的信息，如果是，则可选地识别第二个 要在其上镜像数据的目标设备。 将单个硬件I / O控制块传输到主机适配器集成电路后，主机适配器集成电路确定硬件I / O控制块是否指定镜像事务。 如果指定了镜像事务，则主机适配器集成电路使用第一个硬件I / O控制块中的信息为第二个目标设备生成第二个硬件I / O控制块。 当两个硬件I / O控制块的执行完成时，主机适配器集成电路向主机系统提供单个完成通知。

公开(公告)号：US06845439B1

公开(公告)日：2005-01-18

申请号：US09872830

申请日：2001-05-31

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F12/08 ,  G06F13/38

CPC分类号： G06F13/385

摘要： A method for accessing hardware I/O control blocks, which are stored in an hardware I/O control block array, by a parallel SCSI host adapter addresses one page in a plurality of pages of the hardware I/O control block array for the parallel SCSI host adapter using a first portion of a hardware I/O control block array pointer in the parallel SCSI host adapter. The one page includes a plurality of storage sites for hardware I/O control blocks. A hardware I/O control block stored in the one page is addressed using a second portion of the hardware I/O control block array pointer in the parallel SCSI host adapter. Addressing the hardware I/O control block stored in the one page includes using a tag supplied by a reconnecting SCSI target as the second portion.

摘要翻译： 用于通过并行SCSI主机适配器访问存储在硬件I / O控制块阵列中的硬件I / O控制块的方法来寻址用于并行的硬件I / O控制块阵列的多个页面中的一页 SCSI主机适配器使用并行SCSI主机适配器中硬件I / O控制块数组指针的第一部分。 该页面包括用于硬件I / O控制块的多个存储站点。 存储在一页中的硬件I / O控制块使用并行SCSI主机适配器中的硬件I / O控制块数组指针的第二部分来寻址。 存储在一页中的硬件I / O控制块的寻址包括使用由重新连接的SCSI目标提供的标签作为第二部分。

公开(公告)号：US06978336B1

公开(公告)日：2005-12-20

申请号：US10002869

申请日：2001-12-05

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F13/14 ,  H04L12/66

CPC分类号： G06F3/0658 ,  G06F3/061 ,  G06F3/0674 ,  H04L12/66

摘要： A parallel SCSI host adapter uses an expanded SCB array for both non-Packetized and Packetized SCSI Protocols. The expanded SCB array is partitioned into a low page and a high page. SCBs for non-Packetized SCSI Protocol target devices that utilize a one-byte tag are stored in the low page and the storage site number is the tag. SCBs for Packetized SCSI Protocol target devices that utilize a multi-byte tag are stored on both the low page and the high page. For Packetized SCSI Protocol target devices, the two-bytes required to identify the page and the number of the storage site in the page are used as the tag. SCBs for Packetized SCSI Protocol target devices are stored in the low page only if there are no available storage sites in the high page.

摘要翻译： 并行SCSI主机适配器使用扩展的SCB阵列用于非分组化和分组化SCSI协议。 扩展的SCB阵列被分为低页和高页。 使用单字节标签的非分组化SCSI协议目标设备的SCB存储在低页面中，存储站点号是标签。 使用多字节标签的分组化SCSI协议目标设备的SCB存储在低页面和高页面上。 对于分组化SCSI协议目标设备，标识页面所需的两个字节和页面中存储站点的数量用作标签。 仅当高页面中没有可用的存储站点时，用于打包SCSI协议目标设备的SCB才被存储在低页面中。

公开(公告)号：US06934771B1

公开(公告)日：2005-08-23

申请号：US10779417

申请日：2004-02-12

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F3/06 ,  G06F11/20 ,  G06F13/00 ,  H04B1/74 ,  H04L1/22 ,  H05K10/00

CPC分类号： G06F11/2087 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0689 ,  Y10S707/99953 ,  Y10S707/99955

摘要： A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

摘要翻译： 单个主机适配器硬件I / O控制块包含用于指定从主机系统到第一目标设备的数据传输的信息，以及指定是否要镜像数据的信息，如果是，则可选地识别第二个 要在其上镜像数据的目标设备。 将单个硬件I / O控制块传输到主机适配器集成电路后，主机适配器集成电路确定硬件I / O控制块是否指定镜像事务。 如果指定了镜像事务，则主机适配器集成电路使用第一个硬件I / O控制块中的信息为第二个目标设备生成第二个硬件I / O控制块。 当两个硬件I / O控制块的执行完成时，主机适配器集成电路向主机系统提供单个完成通知。

公开(公告)号：US06769037B1

公开(公告)日：2004-07-27

申请号：US09745034

申请日：2000-12-20

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F300

CPC分类号： G06F13/4059

摘要： A method for flow control by a SCSI system using a Packetized SCSI Protocol includes transferring a data packet information unit in a Packetized SCSI Protocol Data Out phase between a SCSI initiator and a SCSI target over a SCSI bus. The method also includes generating a signal on said SCSI bus by said SCSI target in said Packetized SCSI Protocol Data Out phase to indicate whether another data packet information unit is to be accepted in said Packetized SCSI Protocol Data Out phase by said SCSI Target.

摘要翻译： 通过使用分组化SCSI协议的SCSI系统进行流量控制的方法包括通过SCSI总线在SCSI发起器和SCSI目标之间的分组化SCSI协议数据输出阶段中传送数据分组信息单元。 该方法还包括在所述分组化SCSI协议数据输出阶段中由所述SCSI目标在所述SCSI总线上产生信号，以指示所述SCSI目标在所述分组化SCSI协议数据输出阶段是否接受另一个数据分组信息单元。

公开(公告)号：US06728815B1

公开(公告)日：2004-04-27

申请号：US09745105

申请日：2000-12-20

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F1300

CPC分类号： G06F13/4269 ,  Y10S370/912

摘要： A method for data streaming by a SCSI target includes transmitting a data packet information unit in a Packetized SCSI Protocol Data In phase. The SCSI target also generates a signal during the Packetized SCSI Protocol Data In phase to indicate whether a header packet information unit or another data packet information unit is to be transmitted next in the Packetized SCSI Protocol Data In phase.

摘要翻译： 用于由SCSI目标进行数据流传输的方法包括在分组化SCSI协议数据同步阶段中发送数据分组信息单元。 SCSI目标还在分组化SCSI协议数据同步期间生成信号，以指示在分组化SCSI协议数据同步阶段中是否要发送报头分组信息单元或另一数据分组信息单元。

公开(公告)号：US06701385B1

公开(公告)日：2004-03-02

申请号：US10051907

申请日：2002-01-16

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F1200

CPC分类号： G06F11/2087 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/0689 ,  Y10S707/99953 ,  Y10S707/99955

摘要： A single host adapter hardware I/O control block contains information used to specify a transfer of data from a host system to a first target device and in addition information that specifies whether the data is to be mirrored, and if so, optionally identifies a second target device on which the data is to be mirrored. After transferring the single hardware I/O control block to the host adapter integrated circuit, the host adapter integrated circuit determines whether the hardware I/O control block specifies a mirrored transaction. If a mirrored transaction is specified, the host adapter integrated circuit generates a second hardware I/O control block for the second target device using the information in the first hardware I/O control block. When the execution of both hardware I/O control blocks is complete, the host adapter integrated circuit provides a single completion notification to the host system.

摘要翻译： 单个主机适配器硬件I / O控制块包含用于指定从主机系统到第一目标设备的数据传输的信息，以及指定是否要镜像数据的信息，如果是，则可选地识别第二个 要在其上镜像数据的目标设备。 将单个硬件I / O控制块传输到主机适配器集成电路后，主机适配器集成电路确定硬件I / O控制块是否指定镜像事务。 如果指定了镜像事务，则主机适配器集成电路使用第一个硬件I / O控制块中的信息为第二个目标设备生成第二个硬件I / O控制块。 当两个硬件I / O控制块的执行完成时，主机适配器集成电路向主机系统提供单个完成通知。

公开(公告)号：US06408354B1

公开(公告)日：2002-06-18

申请号：US09275652

申请日：1999-03-24

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F1320

CPC分类号： G06F13/28 ,  G06F13/387 ,  G06F13/4027

摘要： A parallel host adapter that interfaces two I/O buses includes at least two independent data channels, a receive data channel and a send data channel. The receive data channel supports at least two data contexts. The parallel host adapter also includes an administrative information channel that couples one of the I/O buses to a memory where administrative information for the parallel host adapter is stored. The send data channel includes a send buffer memory, and a data transfer engine. The data transfer engine is coupled to a first port of the send buffer memory and to a first I/O bus coupled to the parallel host adapter. The send buffer memory is a single data context buffer memory. The receive data channel includes a receive buffer memory, and another data transfer engine. The another data transfer engine is coupled to the first I/O bus and to a first port of the receive buffer memory. Data for a first data context is transferred from the second I/O bus to the receive buffer memory through a second port of the receive buffer memory. The data in the first data context is transferred from the receive buffer memory to the first I/O bus by the another data transfer engine. As this is happening, data from a second data context can be transferred from the second I/O bus to the receive buffer memory. Also, as the receive buffer memory is emptying, the send buffer memory may be receiving data.

摘要翻译： 接口两个I / O总线的并行主机适配器包括至少两个独立的数据通道，接收数据通道和发送数据通道。 接收数据信道支持至少两个数据上下文。 并行主机适配器还包括管理信息通道，其将一个I / O总线耦合到存储并行主机适配器的管理信息的存储器。 发送数据信道包括发送缓冲存储器和数据传输引擎。 数据传输引擎耦合到发送缓冲存储器的第一端口和耦合到并行主机适配器的第一I / O总线。 发送缓冲存储器是单个数据上下文缓冲存储器。 接收数据信道包括接收缓冲存储器和另一数据传输引擎。 另一数据传输引擎耦合到第一I / O总线和耦合到接收缓冲存储器的第一端口。 第一数据上下文的数据通过接收缓冲存储器的第二端口从第二I / O总线传送到接收缓冲存储器。 第一数据上下文中的数据由另一数据传输引擎从接收缓冲存储器传送到第一I / O总线。 正如这种情况，来自第二数据上下文的数据可以从第二I / O总线传送到接收缓冲存储器。 而且，当接收缓冲存储器被清空时，发送缓冲存储器可能正在接收数据。

公开(公告)号：US06253272B1

公开(公告)日：2001-06-26

申请号：US09088810

申请日：1998-06-02

申请人： B. Arlen Young

发明人： B. Arlen Young

IPC分类号： G06F1314

CPC分类号： G06F9/4418 ,  G06F9/4486 ,  G06F13/4027

摘要： A method for suspending and resuming execution of firmware routines facilitates high speed concurrent processing within a multi-tasking integrated circuit that interfaces a first input/output (I/O) bus with a second input/output bus. The method uses a single instruction in a first executing routine to save a return address, and to transfer execution to a second routine. Similarly, a single return instruction in the second routine is used to restore the return address and to transfer execution from the second routine to the first routine. The use of single instructions in the two routines reduces the silicon area required to store the firmware, and enhances execution performance.

摘要翻译： 一种用于暂停和恢复执行固件例程的方法有助于将第一输入/输出（I / O）总线与第二输入/输出总线接口的多任务集成电路中的高速并发处理。 该方法在第一执行例程中使用单个指令来保存返回地址，并将执行转移到第二程序。 类似地，第二例程中的单个返回指令用于恢复返回地址并将执行从第二例程传送到第一例程。 在两个例程中使用单个指令可减少存储固件所需的硅面积，并提高执行性能。